Design flow for shrinking circuits having non-shrinkable IP layout

Abstract

A method for processing an integrated circuit is provided. The method includes providing a first integrated circuit having a first scale, wherein the first integrated circuit comprises a shrinkable circuit comprising a first intellectual property (IP) layout, and a non-shrinkable circuit comprising a second IP layout; and generating a second integrated circuit having a second scale smaller than the first scale. The step of generating the second integrated circuit includes shrinking the shrinkable integrated circuit to the second scale. The method further includes merging the second IP layout with the non-shrinkable circuit to generate a final integrated circuit.

Description

[0001]This application claims the benefit of U.S. Provisional Application Ser. No. 60 / 906,794, filed on Mar. 13, 2007, entitled “Shrink Design Flow with Don't Touch Critical (or Legacy) IP Layout,” which application is hereby incorporated herein by reference.TECHNICAL FIELD[0002]This invention relates generally to the manufacture of integrated circuits, and more particularly to the shrinking of integrated circuits between different technology generations.BACKGROUND[0003]In order to incorporate more functions and achieve better performance and less cost, integrated circuits are formed with increasingly smaller dimensions. However, there are legacy circuits that have already been designed with greater dimensions. It is not cost effective to redesign these circuits for smaller dimensions, and these circuits were typically shrunk before they are implemented on silicon wafers. Conventionally, foundries performed the task of shrinking integrated circuits.[0004]Since the performances of in...

AI Technical Summary

Benefits of technology

The present invention provides a method for processing an integrated circuit that includes a shrinkable circuit and a non-shrinkable circuit. The method involves generating a second integrated circuit with a smaller scale than the first scale, by shrinking the shrinkable circuit to the second scale. The second integrated circuit is then merged with the non-shrinkable circuit to generate the final integrated circuit. This method reduces the adverse effects caused by shrinking non-shrinkable circuits and ensures better accuracy and efficiency in the production of integrated circuits.

Problems solved by technology

It is not cost effective to redesign these circuits for smaller dimensions, and these circuits were typically shrunk before they are implemented on silicon wafers.

This creates a dilemma.

Since these non-shrinkable integrated circuits are often integrated in the same semiconductor chips with shrinkable integrated circuits, whose performances are not affected by their dimensions, the integrated circuits for a semiconductor chip cannot be uniformly shrunk, and efforts are needed to shrink only the shrinkable circuits, while keeping the non-shrinkable circuits intact.

The conventional methods for shrinking integrated circuits suffer drawbacks, however.

First, even if the non-shrinkable circuits are magnified and then shrunk in a same scale, the resulting dimensions and locations of the final circuits may not be exactly the same as in the original design.

This is due to the snapping of integrated circuits to grids, which causes the change in the size and / or location of integrated circuit components.

The change in dimensions may cause performance drift.

Second, GDS files are typically hierarchical with a plurality of levels.

This causes the handling time to be longer.

Third, the adverse change in the dimensions of integrated circuits due to the snapping causes device mismatching.

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