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Method and structure for avoiding hot carrier degradation and soft leakage damage to ESD protection circuit

a protection circuit and hot carrier technology, applied in the field of esd protection devices and their protection against hot carrier degradation, can solve the problems of gate oxide hcd, hot carrier degradation (hcd) and soft leakage, and achieve the effects of reducing hot carrier degradation, reducing hcd, and reducing curren

Inactive Publication Date: 2011-04-19
NAT SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0008]Further, according to the invention, there is provided a method of reducing hot carrier degradation in an ESD protection circuit, comprising the use of a dynamic driver in conjunction with a triggering clamp. The triggering clamp may be a GGNMOS, LVTSCR, or BJT device. Typically the dynamic driver includes a RC circuit. Thus the reduction in HCD is achieved by decreasing the current during an RC delay time.
[0009]Further, according to the invention there is provided a method of achieving early triggering in a triggering ESD protection device, comprising providing a RC circuit connected to a controlling electrode of the triggering device. This reduces the triggering voltage, thus providing early triggering.

Problems solved by technology

However, they typically have high-triggering voltage levels and display breakdown characteristics that are process sensitive and in most cases, result in degradation, especially after exposure to multiple ESD pulses.
A particular problem experienced by triggering clamps is so-called hot carrier degradation (HCD) and soft leakage.
In the case of low leakage circuits, these voltage levels may be stored for a long time thereby causing long term overload, causing HCD of the gate oxide.

Method used

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  • Method and structure for avoiding hot carrier degradation and soft leakage damage to ESD protection circuit
  • Method and structure for avoiding hot carrier degradation and soft leakage damage to ESD protection circuit
  • Method and structure for avoiding hot carrier degradation and soft leakage damage to ESD protection circuit

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Embodiment Construction

[0020]FIG. 5 shows one implementation of the invention, in which a NMOS device 50 is connected between Vdd and VSS and has its gate connected to ground through a resistor 52. The NMOS device 50 serves as the triggering circuit, the controlling electrode of which is held in an on-state during a RC time defined by a driver circuit that includes a resistor 54 and a capacitor 56. The NMOS device 50 is connected to the RC circuit through a PMOS device 58 and the resistor 52. Initially, the dynamic driver presents an essentially discharged capacitor 56. The resistor 54 and capacitor 56 are chosen to provide a delay time that is greater than the duration of a ESD pulse. During the voltage increase of the ESD pulse, the triggering structure remains in an open channel state. This results in early triggering since the triggering voltage is decreased due to the increase of the gate bias. Notwithstanding this benefit of a decreased triggering voltage, the operating characteristics of the circui...

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PUM

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Abstract

In a ESD protection device, hot carrier degradation and soft leakage are reduced by introducing a dynamic driver that includes a RC circuit for keeping the triggering circuit of the ESD device in an on-state for a certain period of time. This allows the current through the ESD protection device to be reduced during the RC delay time.

Description

FIELD OF THE INVENTION[0001]The invention relates to ESD protection devices and their protection against hot carrier degradation.BACKGROUND OF THE INVENTION[0002]In order to avoid damage to electronic circuits during electrostatic discharge (ESD) protection circuits have been devised to shunt current to ground and limit exposure to excessive voltages. A variety of devices have been developed including grounded gate NMOS, LVTSCR, and BJT triggering clamps. BJTs typically rely on avalanche breakdown and may be enhanced through the use of zener diodes to trigger the base of the BJT. These triggering clamps typically have relatively small dimensions with an active device width of 100-500 mm. However, they typically have high-triggering voltage levels and display breakdown characteristics that are process sensitive and in most cases, result in degradation, especially after exposure to multiple ESD pulses.[0003]Normal operation mode clamps such as Merrill clamps are also known. These diff...

Claims

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Application Information

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IPC IPC(8): H02H3/22
CPCH03K19/00315H01L27/0266
Inventor VASHCHENKO, VLADISLAVHOPPER, PETERCONCANNON, ANN
Owner NAT SEMICON CORP
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