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Memory cell

a memory cell and cell technology, applied in the field of memory cells, can solve the problems of difficult application of resistance change elements, and achieve the effect of stable erasing resistance independent of repetition ra

Active Publication Date: 2012-10-23
SONY SEMICON SOLUTIONS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent text describes a memory cell that can control the resistance value of a resistance change element, such as a resistance change layer, to achieve a high or low resistance state. The cell includes an MOS transistor, a storage element, and a nonlinear resistance element, which has a nonlinear current-voltage characteristic opposite to that of the MOS transistor. By applying a voltage to the nonlinear resistance element, the resistance change layer can be controlled to have a value within a range where current is not significantly limited by the MOS transistor. This allows for a stable erasing resistance independent of the repetition rate. The nonlinear resistance element can be electrically connected in parallel or series with the storage element to achieve the desired resistance value. The technical effect of this invention is to provide a memory cell with a controlled resistance value, regardless of the nonlinear current-voltage characteristic of the MOS transistor, and a stable erasing resistance independent of the repetition rate.

Problems solved by technology

However, a current-voltage characteristic of a variable resistance element is not ohmic, and is nonlinear in such a manner that current is proportional to voltage raised to a power being larger than one.
This has caused a problem that when a voltage applied to the resistance change memory is increased, the resistance change element is not easily applied with a voltage necessary for changing the element into a high or low resistance state due to current limitation of the transistor.

Method used

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first embodiment

[0054]A storage device according to a first embodiment of the invention includes memory cells 1 arranged in matrix as storage units. FIG. 1 shows the memory cell 1 of the storage device in an enlarged manner. The memory cell 1 is formed by connecting a storage element 10, a nonlinear resistance element 20, and an MOS (Metal Oxide Semiconductor) transistor 30 in series.

[0055]FIG. 2 shows an example of a sectional configuration of the storage element 10. The storage element 10 is formed by stacking an electrode 11, an interlayer insulating film 12, a resistance change layer 13, an ion source layer 14, and an electrode 15 in this order. The electrode 11 is electrically connected to a source line S, and the electrode 15 is electrically connected to a drain (not shown) of the MOS transistor 30 via the nonlinear resistance element 20. A source (not shown) of the MOS transistor 30 is electrically connected to a bit line B, and a gate (not shown) of the MOS transistor 30 is electrically con...

second embodiment

[0075]A storage device according to a second embodiment of the invention includes memory cells 2 arranged in matrix as storage units. FIG. 7 shows the memory cell 2 of the storage device in an enlarged manner. The memory cell 2 is formed by connecting a storage element 40 and an MOS transistor 30 in series. FIG. 8 shows an example of a sectional configuration of the storage element 40. The storage element 40 is formed by stacking an electrode 11, a voltage control film 41, a resistance change layer 13, an ion source layer 14, and an electrode 15 in this order. That is, the memory cell 2 corresponds to the memory cell 1 of the first embodiment in which the nonlinear resistance element 20 is removed from the memory cell 1, and the interlayer insulating film 12 is replaced by the voltage control film 41 in the storage element 10 of the first embodiment.

[0076]As shown in FIG. 8, the voltage control film 41 has an opening 41A running through the voltage control film 41, and is contacted ...

example of second embodiment

[0083]FIG. 9 shows a schematic configuration of an apparatus where the memory cell 2 of the second embodiment has a switch element 50 on a bit line B, and has an ammeter 60 in parallel with the switch element 50. In the example, resistance distribution in the memory cell 2 was measured using the apparatus. At that time, the voltage control film 41 was configured of SiWN, and a Si / W ratio of SiWN was appropriately adjusted so that a resistance value of the voltage control film 41 was 1 MΩ. In addition, resistance distribution in the memory cell 2 was measured using various voltage waveforms (a bit line voltage VB, a word line voltage VW, and a source line voltage VS) shown in (A) to (C) of FIG. 10.

[0084]In a writing cycle, the bit line voltage VB was changed from V1 (3 V) to zero V, the word line voltage VW was changed from zero V to V2 (1.3 V), and the source line voltage VS was kept to V3 (3 V) while pulse width of the bit line voltage VB was 10 μsec. In an erasing cycle, the bit l...

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Abstract

A memory cell is provided, in which a resistance value is appropriately controlled, thereby a variable resistance element may be applied with a voltage necessary for changing the element into a high or low resistance state. A storage element 10, a nonlinear resistance element 20, and an MOS transistor 30 are electrically connected in series. The storage element 10 has a nonlinear current-voltage characteristic opposite to a nonlinear current-voltage characteristic of the MOS transistor 30, and changes into a high or low resistance state in accordance with a polarity of applied voltage. The nonlinear resistance element 20 has a nonlinear current-voltage characteristic similar to the nonlinear current-voltage characteristic of the storage element 10.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]The present application is a national stage of International Application No. PCT / JP2008 / 071531 filed on Nov. 27, 2008 and claims priority to Japanese Patent Application No. 2007-308916 filed on Nov. 29, 2007 the disclosures of which are incorporated herein by reference.BACKGROUND[0002]The present invention relates to a memory cell having a variable resistance element.[0003]An NOR or an NAND flash memory has been typically used as a semiconductor nonvolatile memory for data storage. However, such a flash memory needs a high voltage for writing and erasing, and besides, is limited in number of electrons to be injected into a floating gate. Consequently, limitation in size reduction of the flash memory is pointed out.[0004]At present, a resistance change memory such as PRAM (Phase Change Random Access Memory) or PMC (Programmable Metallization Cell) is proposed as a next-generation nonvolatile memory that may exceed a limit in size reduction...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G11C11/00G11C11/36H10N99/00
CPCG11C13/0004H01L27/101H01L27/2436H01L45/04H01L45/06H01L45/085H01L45/1233H01L45/1266H01L45/142H01L45/143H01L45/144H01L45/145H01L45/146G11C13/00G11C2213/79H10B63/30H10N70/245H10N70/8416H10N70/8822H10N70/8825H10N70/883H10N70/8828H10N70/8833H10N70/826
Inventor YASUDA, SHUICHIROARATANI, KATSUHISAKOUCHIYAMA, AKIRAMIZUGUCHI, TETSUYASASAKI, SATOSHI
Owner SONY SEMICON SOLUTIONS CORP
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