System and method for dynamic data prefetching

Abstract

According to one embodiment of the invention, a method comprises measuring memory access latency for a prefetch cycle associated with a transmission of data from a memory device to a destination device such as a storage device. Hereafter, the prefetch rate is dynamically adjusted based on the measured memory access latency.

Description

FIELD[0001]Embodiments of the invention relate to the field of data storage, in particular, to a dynamic data prefetching mechanism for storage devices.GENERAL BACKGROUND[0002]For many years, computers are implemented with a processor (e.g. central processing unit “CPU”), semiconductor-based host memory, and one or more storage devices. Typically, the host memory is adapted to store data, such as instructions or other types of digital data for example, which needs to be quickly accessed by the processor. For instance, when the computer is in normal operation, the host memory usually contains main portions of its operating system and some or all of the application programs and related data that are currently being used. One type of host memory is random access memory (RAM) that is located in close physical proximity to the processor of the computer.[0003]In contrast with host memory, a storage device provides a physical medium for storing larger amounts of data that is less frequentl...

AI Technical Summary

Benefits of technology

The invention is about a mechanism for improving the performance of data storage devices by dynamically adjusting the rate at which data is prefetched from the host memory to the storage device. This mechanism takes into account real-time operational conditions, such as changes in memory access latency and the type of interface or communication protocol used by the storage device. By adjusting the prefetch rate in real-time, the mechanism helps to optimize the use of the interconnect between the host and the storage device, reducing latency and improving overall computer performance.

Problems solved by technology

Hence, in order to reduce overall computer costs, the size of host memory is typically limited, which requires data to be frequently transmitted from host memory to the storage device.

During each transmission to the storage device, a time delay is normally experienced.

However, in actual operating conditions, the memory access latency is not a constant value, but varies in response to operational conditions of the computer.

In short, the current prefetch mechanism does not account for real-time operational conditions detected during various prefetch cycles.

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