Multicast address learning in an input/output adapter of a network processor

Abstract

An apparatus for supporting multicast address learning in a network processor includes a task parameter decoder receiving the packet and determining parameters of the packet, a plurality of unlearned address counters recording a number of the packets to be multicast, a correlator determining destination addresses of the packet, a multicast replicator replicating the packet multiple times, and a task generator generating a generated packet with a bitmap and sending out the generated packet to an I / O adaptor over a task ring interface of the network processor. If the packet is unlearned, the unlearned address counter is then incremented and the unlearned packet is sent back to a special queue in the I / O adaptor over the task ring interface with an index to the bitmap for replicating by the multicast replicator, after replicating, the unlearned address counter is decremented. Methods for replicating unlearned / learned multicast packets within a network processor are included.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit of the filing date of U.S. provisional application No. 61 / 580,170, filed Dec. 23, 2011, the teachings of which are incorporated herein in their entireties by reference.[0002]This application is a continuation-in-part, and claims the benefit of the filing date, of U.S. patent application Ser No. 12 / 782,379 filed May 18, 2010, Ser. No. 12 / 782,393 filed May 18, 2010 now U.S. Pat. No. 8,255,644, and Ser. No. 12 / 782,411 filed May 18, 2010 now U.S. Pat. No. 8,407,707, the teachings of which are incorporated herein in their entireties by reference.[0003]The subject matter of this application is related to U.S. patent application Ser. No. 12 / 430,438 filed Apr. 27, 2009, Ser. No. 12 / 729,226 filed Mar. 22, 2010, Ser. No. 12 / 729,231 filed Mar. 22, 2010, Ser. No. 12 / 963,895 filed Dec. 9, 2010, Ser. No. 12 / 971,742 filed Dec. 17, 2010, Ser. No. 12 / 974,477 filed Dec. 21, 2010, Ser. No. 12 / 975,823 filed Dec. 22, 2010, ...

AI Technical Summary

Benefits of technology

The invention provides an apparatus for analyzing and processing network packets. It includes a task parameter decoder, a multicast replicator, and a task generator. The task parameters decoder analyzes the packet and determines its type (multicast or unicast) and the destination addresses. The multicast replicator receives the destination addresses and replicates the packet multiple times based on the number of destination addresses. The task generator generates a new packet with a bitmap based on the destination addresses and sends it out to the network processor for further processing. This invention reduces bandwidth usage and improves efficiency for transmitting network packets.

Problems solved by technology

Early types of network processors were based on software-based approaches with general-purpose processors, either singly or in a multi-core implementation, but such software-based approaches are slow.

Further, increasing the number of general-purpose processors diminished performance improvements, or actually slowed down overall network processor throughput.

However, significant software overhead is involved in those cases where multiple accelerator actions might occur in sequence.

This fixed sequence might add significant overhead to packet processing and has limited flexibility to handle new protocols, limiting the advantage provided by using the accelerators.

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