Field-effect transistor (FET) with source-drain contact over gate spacer

Abstract

A field-effect transistor (FET) and methods for fabricating such. The FET includes a substrate having a crystalline orientation, a source region in the substrate, and a drain region in the substrate. Gate spacers are positioned over the source region and the drain region. The gate spacers include a gate spacer height. A source contact physically and electrically contacts the source region and extends beyond the gate spacer height. A drain contact physically and electrically contacts the drain region and extends beyond the gate spacer height. The source and drain contacts have the same crystalline orientation as the substrate.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims priority under 35 U.S.C. §120 to U.S. patent application Ser. No. 13 / 920,044 filed Jun. 17, 2013, the entire text of which is specifically incorporated by reference herein.BACKGROUND[0002]The present invention relates to transistor design, and more particularly, to a novel field-effect transistor (FET) design.[0003]FETs are a type of transistor that have source, drain, and gate terminals. Typically, integrated circuits include many FETs on a single substrate. As circuits become miniaturized, the size of FETs become smaller and smaller. Smaller FETs tend to have higher parasitic contact resistance due to a smaller contact area in the source-drain region. The parasitic contact resistance can dominate circuit delay during the circuit's operation.BRIEF SUMMARY[0004]Accordingly, one example aspect of the present invention is a method for constructing a field-effect transistor (FET). The method includes forming a source ...

AI Technical Summary

Benefits of technology

The present invention relates to a method for constructing a field-effect transistor (FET) and a transistor array. The technical effect of the invention is to provide a method for making a FET with precise placement of gate spacers and contacts, which results in improved performance and stability of the transistor. The FET includes a substrate with a crystalline orientation and source and drain regions. The gate spacers are positioned over the source and drain regions and have a height that dictates the placement of contacts. The contacts physically and electrically contact the source and drain regions and extend beyond the gate spacer height. The transistor array includes a substrate with a crystalline orientation and multiple FETs with precise placement of gate spacers and contacts. The technical effect is to create a more efficient and reliable field-effect transistor with improved performance and stability.

Problems solved by technology

As circuits become miniaturized, the size of FETs become smaller and smaller.

The parasitic contact resistance can dominate circuit delay during the circuit's operation.

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