Method and apparatus for generating a pulse

Abstract

A circuit for generating a pulse with minimal delay after receiving a trigger signal includes a passgate, a gating circuit, and a reset circuit. The passgate is enabled by control signals received at the gating circuit having a trigger signal as one of the control signals. The trigger signal is also presented as an input to the passgate. When enabled, the passgate propagates the trigger signal to an output. A predetermined time after the trigger signal appears at the passgate input, a passgate control signal is turned off, thereby preventing the trigger signal from further passing through the passgate. The reset circuit is then turned on, which pulls the signal at the output of the passgate to a reference voltage, ending the pulse. Once the pulse is generated, it can be rectified and further combined with other signals to produce signals used in other parts of the circuit.

Description

TECHNICAL FIELD[0001]This invention relates to clocked integrated circuits, and more particularly, to a method and apparatus to generate a pulse with minimal delay after receiving a trigger signal.BACKGROUND OF THE INVENTION[0002]Clock signals are used by a wide variety of digital circuits to control the timing of various events occurring during the operation of the digital circuits. For example, clock signals are used to designate when command signals, data signals, and other signals used in memory devices and other computer components are valid and can thus be used to control the operation of the memory device or computer system. For instance, a clock signal can be used to develop sequential column addresses when an SDRAM is operating in burst mode.[0003]Generating a signal using a clocked signal as an input can be difficult to coordinate. Some of the signals generated may need to be timed to either a rising or falling edge of a clock signal, or may become operative only after a g...

AI Technical Summary

Benefits of technology

[0016]In yet another embodiment, the gating circuit changes the passgate from a passing state to a blocking state when the gating circuit receives a control signal derived from

Problems solved by technology

Generating a signal using a clocked signal as an input can be difficult to coordinate.

One of the problems with generating signals from a clock signal is a time delay caused by additional circuitry needed for the coordination.

Each component used in a circuit (logic gate, buffer, amplifier, etc.) introduces a time delay when producing a signal.

Capacitive loading, internal resistance, and other factors cause this delay.

As stated above, because of capacitance, resistance, and other factors within a logic device, there is a delay between the time a signal is presented on the input to the logic device and when a signal is generated at the output of the logic device.

Second, the output pulse signal P1 lacks the driving capability needed by the circuit.

The signal I2 has the correct orientation to become the IOPU signal, but still lacks enough drive capacity.

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