Nonvolatile semiconductor memory device

a semiconductor memory and non-volatile technology, applied in semiconductor devices, digital storage, instruments, etc., can solve the problems of inability to implement desired switching operations and unstable oscillation, and achieve the effect of reducing circuit size and reducing writing tim

Active Publication Date: 2015-01-20
XENOGENIC DEV LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent describes a nonvolatile semiconductor memory device that can perform stable bipolar and unipolar switching operations using voltage pulses of both positive and negative polarities. By setting proper load resistive characteristics and correlating the threshold voltages of the resistive elements, the circuit can have a simple structure, reduced chip size, and lower manufacturing cost. The device also reduces the effect of sneak path current from adjacent memory cells and shortens the writing time.

Problems solved by technology

This results in an unstable oscillation phenomenon that the resistive characteristics of a variable resistive element keep on changing between the high resistance state (characteristics A) and the low resistance state (characteristics B).
In sum, application of voltage to a variable resistive element alone without setting a current compliance value could not implement desired switching operations.

Method used

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Experimental program
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first embodiment

[0211]A description will be made of a first embodiment (hereinafter occasionally referred to as the “present embodiment”) according to a manufacturing method of the device of the present invention, with reference to FIGS. 20 to 36. FIG. 20 is a schematic view showing a memory cell to be formed in the present embodiment, and FIG. 21 is a plan view showing the memory cell. The device of the present invention manufactured in the present embodiment is configured by a first wiring including a tungsten (W) layer and a TiN adhesive layer, a memory cell portion including a TiN barrier metal, a resistance lowering layer formed of TiN-type polysilicon, a TiN lower electrode, and a TiOxNy variable resistor, and a second wiring including an upper electrode and a tungsten layer. In addition, FIGS. 22 to 32 show the manufacturing method of the present embodiment in the order of steps. In FIGS. 22 to 32, figures A each show a vertical sectional view taken along line X-X′ in FIG. 20, and figures B ...

second embodiment

[0233]A description will be made of a second embodiment (hereinafter occasionally referred to as the “present embodiment”) according to the manufacturing method of the device of the present invention, with reference to FIGS. 37 to 49. FIG. 37 is a schematic view showing a memory cell to be formed in the present embodiment, and FIG. 38 is a plan view showing the memory cell. The device of the present invention to be manufactured in the present embodiment is configured by a first wiring layer including an N+ layer and an N− layer formed in a P-type silicon substrate, a memory cell portion including a TiN lower electrode and a TiON variable resistor, a second wiring including a TiN layer serving as an upper electrode and a adhesive layer, and a W layer. In addition, FIGS. 39 to 46 show the manufacturing method of the present embodiment in the order of steps. In FIGS. 39 to 46, figures A each show a vertical sectional view taken along line X-X′ in FIGS. 38, and figures B each show a ver...

third embodiment

[0245]A description will be made of a third embodiment (hereinafter occasionally referred to as the “present embodiment”) according to the manufacturing method of the device of the present invention, with reference to FIGS. 50 to 60. FIG. 50 is a schematic view showing a memory cell formed in the present embodiment, and FIG. 51 is a plan view showing the memory cell. The device of the present invention to be manufactured in the present embodiment is configured by a first wiring including a W layer and a TiN adhesive layer, a memory cell portion including a TiN barrier metal, a TiN-type polysilicon resistance lowering layer, a TiN lower electrode and a TiON variable resistor, and a second wiring including an upper electrode, a adhesive layer and a W layer. In addition, FIGS. 52 to 58 show the manufacturing method of the present embodiment in the order of steps. In FIGS. 52 to 58, figures A each show a vertical sectional view taken along line X-X′ in FIG. 51, and figures B each show a...

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Abstract

A nonvolatile semiconductor memory device include: a two terminal structured variable resistive element, wherein resistive characteristics defined by current-voltage characteristics at both ends transit between low and high resistance states stably by applying a voltage satisfying predetermined conditions to the both ends. A transition from the low resistance state to the high resistance state occurs by applying a voltage of a first polarity whose absolute value is at or higher than first threshold voltage, and the reverse transition occurs by applying a voltage of a second polarity whose absolute value is at or higher than a second threshold voltage. A load circuit is connected to the variable resistive element in series having an adjustable load resistance. A voltage generation circuit applies a voltage to both ends of a serial circuit. The variable resistive element can transit between the states by adjusting a resistance of the load circuit.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a Reissue of U.S. Pat. No. 8,023,312 (previously U.S. patent application Ser. No. 12 / 515,286, filed May 18,2009), which is a National Phase filing under 35 U.S.C. §371 of International Application No. PCT / JP2007 / 071502 filed on Nov. 5, 2007, and which claims priority to Japanese Patent Application No. 2006-331689 filed on Dec. 8, 2006.TECHNICAL FIELD[0002]The present invention relates to a nonvolatile semiconductor memory device and more particularly, to a nonvolatile semiconductor memory device including a variable resistive element whose resistive characteristics vary in accordance with application of voltage.BACKGROUND ART[0003]A nonvolatile semiconductor memory device typified by a flash memory is used in various fields such as computers, communications, measurement devices, automatic control units and household appliances used around individuals, as an information recording medium that is large in capacity and sma...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G11C11/00
CPCH01L27/2463G11C2213/15H01L45/04G11C13/003H01L27/101G11C2213/71H01L45/146H01L45/145H01L45/1233H01L27/2481G11C2213/77G11C2213/32H01L27/2409H01L45/1633G11C2213/34G11C2213/76G11C2213/72G11C13/0007G11C2213/79H10B63/20H10B63/80H10B63/84H10N70/20H10N70/826H10N70/8833H10N70/883H10N70/028
Inventor YAMAZAKI, SHINOBUHOSOI, YASUNARIAWAYA, NOBUYOSHISATO, SHINICHITANAKA, KENICHI
Owner XENOGENIC DEV LLC
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