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Method of forming semiconductor patterns

a semiconductor pattern and pattern technology, applied in semiconductor/solid-state device manufacturing, basic electric elements, electric devices, etc., can solve the problems of difficult control of the uniform amount of shrinking of such a photo resist shrink step or trimming step, higher and collapsing of photo resist lines, so as to reduce the amount of pr footing and reduce the chance of patterning failure. , the effect of increasing the trimming ra

Active Publication Date: 2018-12-18
ASM IP HLDG BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention aims to find solutions to problems that arise while performing a trimming step in the manufacturing process of a semiconductor device. The invention offers a Spacer-Defined Double Patterning process for 3X nm and below that avoids such problems. In one embodiment, the invention provides a direct plasma-based PR trimming process with reduced PR footing that may occur during the process. This is achieved by a two-step process of PR trimming followed by deposition of SiO2 film. The process utilizes a direct plasma generated between a susceptor electrode and an opposing electrode to activate ions and accelerate them in a vertical direction towards the substrate, resulting in higher trimming rate towards vertical direction than horizontal direction on the PR, and reducing the PR footing in the bottom of the PR.

Problems solved by technology

If the target Critical Dimension of lines is getting smaller than 30 nm, it will become difficult to control the uniformity of the amount of shrinking of such a photo resist shrink step or trimming step.
Furthermore, there is a higher chance of patterning failure due to the leaning or collapsing of photo resist line due to the weak footing of the photo resist line when the photo resist line becomes narrower by the trimming.

Method used

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  • Method of forming semiconductor patterns

Examples

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experimental example 1

[0037]A SiO2 film deposition by PEALD on photo resist template patterns is carried out with the following conditions.

[0038]Metalorganic precursors or halosilane precursors containing Si can be used as Si precursors. In the present invention, for example, SiH2[N(C2H5)2]2 was used as a Si precursor. Susceptor temperature for heating substrate varied from room temperature to 200 degree C., preferably the susceptor temperature was 50 degree C. During deposition, process pressure is maintained in a range from 1 to 10 Torr, preferably at a value of about 3 Torr. RF plasma power is in a range from 10 to 1000 W, preferably at a value of about 200 W.

[0039]Gas flow condition is as follows.[0040]Source Ar flow rate for carrying bubbled precursor into reactor: 200 sccm[0041]Temperature of precursor container: 60° C.[0042]O2 reactant flow rate: 50 sccm[0043]Reactant Ar flow rate for flowing into reactor with oxygen: 200 sccm[0044]Main Ar flow rate for chamber / gas line purge: 200 sccm[0045]Proces...

experimental example 2

[0051]A SiO2 film deposition by PEALD on photo resist template patterns is carried out with the following conditions.

[0052]Metalorganic precursors or halosilane precursors containing Si can be used as Si precursors. In this invention, SiH2[N(C2H5)2]2 was used as a Si precursor. Susceptor temperature for heating substrate varied from room temperature to 200 degree C., preferably the susceptor temperature was 50 degree C. During deposition, process pressure is maintained in a range from 1 to 10 Torr, preferably at a value of about 3 Torr. RF plasma power is in a range from 10 to 1000 W, preferably at a value of about 100 W to 150 W.

[0053]Gas flow condition:[0054]Source Ar flow rate for carrying bubbled precursor into reactor: 500 sccm[0055]Temperature of precursor container: 60° C.[0056]O2 reactant flow rate: 1000 sccm[0057]Reactant Ar flow rate for flowing into reactor with oxygen: 500 sccm[0058]Main Ar flow rate for chamber / gas line purge: 200 sccm[0059]Reaction space gap between sh...

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Abstract

Semiconductor patterns are formed by performing trimming simultaneously with the process of depositing the spacer oxide. Alternatively, a first part of the trimming is performed in-situ, immediately before the spacer oxide deposition process in the same chamber in which the spacer oxide deposition is performed whereas a second part of the trimming is performed simultaneously with the process of depositing the spacer oxide. Thus, semiconductor patterns are formed reducing PR footing during PR trimming with direct plasma exposure.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit of U.S. Provisional Application No. 61 / 323,918, filed on Apr. 14, 2010, in the United States Patent and Trademark Office, the disclosure of which is incorporated herein in its entirety by reference.BACKGROUND OF THE INVENTION[0002](a) Field of the Invention[0003]The present invention relates to a method of forming semiconductor patterns. More specifically, the present invention relates to a spacer defined double patterning (SDDP) process using a PEALD spacer oxide deposition process having trimming action.[0004](b) Description of the Related Art[0005]Due to the limit of resolution of the immersion ArF lithography, the method of Double Patterning is used in the chip patterning process for 3× nm half pitch and below.[0006]In the art, the method of Spacer Defined Double Patterning, as represented in FIGS. 1A-1D, is as follows. As shown in FIG. 1A, photo resist template patterns 2 are formed on top of a bot...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H01L21/311H01L21/033H01L21/02
CPCH01L21/02222H01L21/02274H01L21/0228H01L21/0337H01L21/0274
Inventor BEYNET, JULIENPARK, HYUNG SANGINOUE, NAOKI
Owner ASM IP HLDG BV
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