The invention discloses a multi-layer gate analog
CMOS process edge stress optimization integration method and a
low voltage coefficient polycrystalline
capacitor. The method steps include: 1) forming an N-type well in a
low voltage coefficient integrated dual polycrystalline
capacitor area, and forming a self-aligned P-type well in an area outside the N-type well; 2) depositing a polycrystalline film layer of a lower
electrode of the
low voltage coefficient integrated dual polycrystalline
capacitor; 3) depositing a first layer of
dielectric of the dual polycrystalline capacitor, and realizing the production of an edge
protection layer of the lower
electrode of the dual polycrystalline capacitor; 4) depositing a capacitor
dielectric layer, and completing the production of a capacitor
dielectric layer structure; the low
voltage coefficient polycrystalline capacitor includes a P-type substrate, a P-type epitaxial layer, an N-type well, a self-aligned P-type well, a
field oxide layer, a sacrificial
oxide layer, a
gate oxide layer, a polycrystalline film layer, a
silicon dioxide
dielectric layer, a capacitor
dielectric layer, a low dielectric coefficient filling film layer, a
metal interconnect film layer, and a protective dielectric
passivation layer outside a top
metal bonding area; the patent improves the edge effect of the dual polycrystalline capacitor and reduces the mechanical stress of the integrated dual polycrystalline capacitor.