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Cascaded delay locked loop circuit

A technology of delay locked loop and delay circuit, which is applied in the direction of automatic power control, angle demodulation through phase difference detection, electrical components, etc., and can solve problems such as unsuitable frequency resolution.

Inactive Publication Date: 2008-10-08
MOTOROLA SOLUTIONS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In order to utilize DLL technology in many Direct Digital Synthesis (DDS) applications, the frequency resolution achievable by known technology is not suitable when considering aspects such as noise, power consumption and excitation generation parameters

Method used

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  • Cascaded delay locked loop circuit
  • Cascaded delay locked loop circuit
  • Cascaded delay locked loop circuit

Examples

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Embodiment Construction

[0018] While the invention has embodiments in many different forms, which have been shown in the drawings and described in detail herein, it should be understood that the embodiments disclosed are merely illustrative of the principles of the invention and are not intended to The invention is limited to the specific embodiments shown and described. In the following description, like reference numerals are used to describe the same, similar or corresponding parts in the several drawings.

[0019] Referring now to FIG. 1, a basic delay locked loop 20 is shown. This circuit is similar to that described in U.S. Patent Application Serial No. 09 / 633,705 entitled "Digital-To-Phase Converter" filed August 7, 2000 by Fredenck Lee Martin (which application is hereby incorporated by reference into this application) ) circuit described in . In this delay locked loop 20, a delay line 24 is formed by a plurality of cascaded controlled delay elements 32, 34, 36 to 38, each delay element 32,...

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PUM

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Abstract

A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.

Description

technical field [0001] The present invention relates generally to the field of delay locked loops. More specifically, the present invention relates to delay locked loops based on frequency synthesizers with improved frequency resolution. Background technique [0002] A delay locked loop (DLL) synthesizer according to the present invention can be used as a frequency synthesizer in many electronic devices such as radiotelephones (eg, cellular telephones), two-way radio transceivers, radio transmitters and radio receivers. Such synthesizers are sometimes called digital-to-phase converters (DPCs). However, to use the DLL effectively in these applications, the frequency output should be accurate and relatively free of spurious components. In many applications, it is also very important to design the DLL architecture to optimize the noise and power dissipation performance parameters. [0003] In order to utilize DLL techniques in many Direct Digital Synthesis (DDS) applications...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03D3/24H03L7/07H03L7/081H03L7/14H03L7/16
CPCH03L7/07H03L7/14H03L7/16H03L2207/08H03L7/0812H03L7/0816H03L7/0818H03L7/00
Inventor 居-国·绢罗伯特·E·斯滕格尔弗莱德里克·L·马丁戴维·E·伯克尔曼
Owner MOTOROLA SOLUTIONS INC