Testing method of memory address line

A technology of memory address and test method, applied in static memory, instruments, etc., can solve the problem of inability to judge the fault of the address line, and achieve the effect of reducing complexity, simple programming, and simple and intuitive operation.

Inactive Publication Date: 2008-10-22
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, step 3 can only determine that the address line is faulty, but cannot determine which one (or several) of the address lines are faulty.

Method used

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  • Testing method of memory address line
  • Testing method of memory address line

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Embodiment Construction

[0094] The present invention locates which address lines have fixed low level and sticky 0-dominant faults with the method of "walking 1" of address lines; uses the method of "walking 0" of address lines to locate which address lines have fixed high level and Sticky 1-dominant type of fault; when performing "walk 1" or "walk 0" test on the address, the data bit corresponding to the test data and the address line to be tested is required to be 0, and the other data bits are 1.

[0095] For the address line "walking 1" test, as shown in Table 4, taking the 8-bit address as an example, first assume that only the same type of connection fault exists, and the fault mode is: a 7 Constantly 0, a 5 and a 4 Short-circuit 0-dominant type, when such a fault occurs, the program will write the test data to the unit with the address 00000000 when writing the test data (when there are multiple address lines faults, it will be written multiple times, if the address line Normally, the addres...

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Abstract

A method for testing address line of storage includes using 'walk 1' or 'walk 0' method to select address unit of storage, writing in test data in address unit, setting the corresponding data bit of said test data to address line to be tested as '0' and the other data bit as '1' , carrying out walk test for all address lines, fetching out data in the first and the last address unit and confirming relevant address line fault according to '0' bit in data.

Description

technical field [0001] The invention relates to a method for testing memory address lines, in particular to a method for accurately locating address line faults by adopting the "step 0" and "step 1" methods. Background technique [0002] At present, the minimum CPU system on a single board generally includes CPU, FLASH and SDRAM and other devices. The CPU is the core of the single board and is used to execute various operations specified by the single board software. FLASH is an electrically erasable memory, even if the board is powered off, the program or data stored in it will not be lost. The CPU can easily read out the content in the FLASH, but only in certain circumstances can it be erased and written. SDRAM is a dynamic memory. After the board is powered off, the programs or data stored in it will be lost, and the CPU can easily read and write SDRAM. The characteristics of these two memories determine that the CPU reads and writes data in FLASH slowly, but reads and ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/00
Inventor 史韦白尤新朱星海
Owner HUAWEI TECH CO LTD
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