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Trench DMOS transistor structure

A trench and gate trench technology, applied in the field of DMOS transistor manufacturing, can solve problems such as limiting the drain-source breakdown voltage of transistors

Inactive Publication Date: 2008-11-26
GEN SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The trenches can extend into the heavily doped substrate 11 to reduce any resistance caused by carrier flow through the lightly doped epitaxial layer 12, but this structure also limits the transistor's drain-to-source breakdown voltage

Method used

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  • Trench DMOS transistor structure
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  • Trench DMOS transistor structure

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Embodiment Construction

[0032] FIG. 3 shows a cross-sectional view of a trench DMOS transistor 100 constructed according to the prior art. A significant advantage of this structure is that it can be used not only in discrete components but also in integrated circuits because it is self-isolated. However, formation of buried layers and deposition of epitaxial layers are required. As shown in FIG. 3 , the trench DMOS transistor 100 includes a substrate 25 , a heavily doped buried region 11 and an epitaxial region 12 . The doping of the epitaxial region 12 is lighter than that of the buried region 11 . While substrate 25 may be N-type or P-type, a P-type substrate is typically preferred when the structure is to be incorporated into an integrated circuit because junction isolated devices can be easily fabricated. The DMOS transistor also includes source regions 16a and 16b and body regions 15a and 15b. As understood by those skilled in the art, body regions 15a and 15b may include deeper heavily doped ...

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Abstract

A trench DMOS transistor structure having a low resistance path to a drain contact located on an upper surface and methods of making the same. The transistor structure comprises: (1) a first region of semiconductor material of a first conductivity type; (2) a gate trench formed within the first region; (3) a layer of gate dielectric within the gate trench; (4) a gate electrode within the gate trench adjacent the layer of gate dielectric material; (5) a drain access trench formed within the first region; (6) a drain access region of conductive material located within the drain access trench; (7) a source region of the first conductivity type within the first region, the source region being at or near a top surface of the first region and adjacent to the gate trench; (8) a body region within the first region below the source region and adjacent to the gate trench, the body region having a second conductivity type opposite the first conductivity type; and (9) a second region of semiconductor material within the first region below the body region. The second region is of the first conductivity type and has a higher dopant concentration than the first semiconductor region. Moreover, the second region extends from the gate trench to the drain access trench and is self-aligned to both the gate trench and the drain access trench.

Description

[0001] related application [0002] This application is a continuation-in-part of U.S. Application Serial No. 09 / 516,285, filed March 1, 2000, and entitled "Trench DMOS Transistor Structure with Low Resistance Path to Drain Contact on Upper Surface." technical field [0003] The present invention generally relates to a MOSFET transistor, and more particularly relates to a method for manufacturing a DMOS transistor with a trench structure. Background technique [0004] A DMOS (Double Diffused MOS) transistor is a transistor of the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) type that uses two sequential diffusion steps aligned on the same edge to form the channel region of the transistor. DMOS transistors are usually high-voltage, high-current devices used as discrete transistors or components in power integrated circuits. DMOS transistors can deliver high current per cell area with low forward voltage drop. [0005] A typical discrete DMOS transistor structu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/76H01L21/336H01L29/06H01L29/08H01L29/417H01L29/78
CPCH01L29/7809H01L29/41766H01L29/7813H01L29/0878H01L29/0696H01L29/0847H01L29/41741H01L29/0653H01L29/66734
Inventor 理查德·A·布朗夏尔
Owner GEN SEMICON