Electrostatic protection circuit in integrated circuit

An electrostatic protection, integrated circuit technology, applied in emergency protection circuit devices, emergency protection circuit devices for limiting overcurrent/overvoltage, static electricity, etc., can solve the problem of reducing the overall protection capability of electrostatic protection circuits, and the inability of GGNMOS devices to be turned on uniformly. and other problems, to achieve the effect of good electrostatic protection and uniform opening

Active Publication Date: 2008-12-24
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The GGNMOS devices in the electrostatic protection circuit of the prior art cannot be turned on uniformly, which reduces the overall protection capability of the electrostatic protection circuit

Method used

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  • Electrostatic protection circuit in integrated circuit
  • Electrostatic protection circuit in integrated circuit
  • Electrostatic protection circuit in integrated circuit

Examples

Experimental program
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Embodiment Construction

[0013] Figure 4 It is a structural schematic diagram of an electrostatic protection circuit for an integrated circuit of the present invention. The invention makes improvements on the basis of the multi-finger parallel GGNMOS circuit of the electrostatic protection circuit in the prior art. like Figure 4 As shown, it includes multiple GGNMOS devices. The source and substrate of the middlemost GGNMOS device 18 are connected to the cathode of a diode 16 , its gate is grounded, and its drain is connected to the previous stage of the internal circuit 2 . The anode of the above-mentioned diode 16 is grounded. Except for the middle GGNMOS18, the drains of the other GGNMOS17 are connected to the internal circuit 2 and the input and output signals 1, their gates are connected to each other and the cathode of the diode 16, and the source and substrate are grounded.

[0014] When the device is working, the electrostatic protection circuit of an integrated circuit of the present inv...

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PUM

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Abstract

The invention discloses an electrostatic protection circuit in an integrated circuit. The electrostatic protection circuit in the integrated circuit of the present invention includes a multi-finger parallel GGNMOS circuit, the drain of the GGNMOS is connected to the previous stage of the internal circuit, and a diode, wherein the most middle GGNMOS source and the substrate are connected to the cathode of the diode , the gate is grounded, the other GGNMOS sources in the multi-finger parallel GGNMOS circuit are grounded, the substrate is grounded, the gates are connected to each other and to the cathodes of the diodes, and the anodes of the diodes are grounded. When ESD occurs, the middlemost The GGNMOS is first turned on, and a bias voltage is generated on the diode to supply gate bias voltages to all GGNMOS gates in other surroundings, so that all GGNMOSs in the protection circuit are turned on evenly. The invention is applicable to the manufacture of integrated circuits.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to an electrostatic protection circuit in an integrated circuit. Background technique [0002] Integrated circuits are easily damaged by static electricity. Generally, an electrostatic protection circuit is designed in the input and output terminals of the circuit or power supply protection to prevent the internal circuit from being damaged by static electricity. GGNMOS (Gate Grounded NMOS, gate grounded N-type metal oxide transistor) is a widely used electrostatic protection structure. figure 1 It is a schematic diagram of the GGNMOS circuit structure. like figure 1 As shown, 3 is GGNOMOS, wherein the drain 4 of the GGNOMOS is connected to the previous stage of the internal circuit 2, and the source 6, the gate 5 and the substrate 7 are all grounded. figure 2 It is the layout of multi-finger parallel GGNMOS circuit. like figure 2 As shown, in order to ensure a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/60H01L23/62H01L27/02H01L27/04H05F3/04H02H9/04
Inventor 徐向明
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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