Microprocessor, apparatus and method for selectively associating store buffer cache line status with response buffer cache line status

Abstract

The present invention relates to a microprocessor, an apparatus and a method for associating a response buffer cache line with a store buffer cache line. The need for coherence among the cache line states of the buffers. The storage buffer includes a plurality of matching bit association units. When a store action requires response buffers to be configured (such as receiving a cache line associated with a store miss written to the configuration cache), the control logic uses the match bit associated with the unit to indicate which response buffer is configured . When a state change event occurs, the control logic updates the cache line state in the allocated response buffer, which is then used to update the cache, thus alleviating the need for the store buffer to maintain the cache line state. If the storage address matches a configured response buffer, the response buffer will be indicated in the matching bit association.

Description

technical field [0001] The present invention relates to the field of caches, and more particularly to the field of utilizing store buffers and response buffers to maintain cache coherency in microprocessors, that is, linking response buffer cache lines to store buffer cache lines Microprocessor and device and method thereof. Background technique [0002] An important part of every operation performed by a microprocessor is reading or writing data from or to memory. Wherein, reading data from the memory usually means loading (load), and writing data usually means storing (store). In general, microprocessors perform loads and stores based on instructions that can access memory. But loads and stores can also be performed by the microprocessor for other necessary operations of the microprocessor, such as loading page table information or evicting a cache line to memory. [0003] Memory access is relatively slow compared to other operations in a microprocessor, so modern micro...

AI Technical Summary

Problems solved by technology

[0016] First, this complexity is error-prone in its design

In other words, it is easy to design bugs in the update logic, but it is difficult to detect bugs in the possible combinations of various conditions and events

Second, complexity means larger control circuitry is required, which will consume excessive chip real resources and affect chip performance

Third, this complexity can affect the critical frequency path, which is related to the frequency speed at which the microprocessor can run

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