Decoupled complementary mask patterning transfer method
A patterning and patterning technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems of not being realized, aggravating the vertical etching depth difference, etc.
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[0023] 1 shows a cross-sectional view of a stack 100 used in a split complementary mask patterning method (eg, in a gate patterning process flow) according to one embodiment of the present invention. Stack 100 includes substrate 102 , gate dielectric 104 over substrate 102 , target layer 106 over gate dielectric 104 , and first hard mask 110 over target layer 106 . Substrate 102 may comprise, for example, a bulk substrate, a bonded wafer substrate (e.g., semiconductor-on-insulator, silicon-on-insulator, germanium-on-insulator, or the like), or other substrates suitable for a particular semiconductor Substrates for device fabrication. Gate dielectric 104 may include, for example, gate oxide, SiON, metal oxide, or other dielectric suitable for a particular semiconductor device fabrication. Target layer 106 may include, for example, a polysilicon layer, a metal layer, a metal oxide layer, a dielectric layer, or other layers suitable for a particular semiconductor device fabricat...
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