Laminated semiconductor device

Abstract

A stacked type semiconductor device comprising: a baseboard having a terminal row formed at an end in which connecting terminals is arranged linearly and having a wiring pattern connected to the connecting terminals and external terminals; semiconductor chips having a pad row in which pads is arranged linearly in parallel to the terminal row and being stacked on the baseboard; and interposer boards having a wiring layer including a plurality of wires arranged in parallel with the same length for connecting between pads of the pad row and connecting terminals of the terminal row.

Description

technical field [0001] The present invention relates to a stacked semiconductor device having a structure in which a plurality of semiconductor chips are stacked. Background technique [0002] In recent years, semiconductor memories such as DRAM (Dynamic Random Access Memory) have been required to have larger capacities in order to achieve higher functionality of devices. The larger the capacity of a semiconductor memory formed on one semiconductor chip, the more microfabrication is required, and thus the possibility of a decrease in yield is higher. Therefore, there have been proposals for a stacked semiconductor device having a structure in which a plurality of semiconductor chips are stacked on a base substrate. For example, by stacking a plurality of DRAM chips and an interface chip for controlling data input and output of each DRAM chip on a base substrate, a small and large-capacity stacked semiconductor device that can be controlled externally can be realized like a ...

AI Technical Summary

Problems solved by technology

Therefore, there is a problem that the wiring efficiency decreases due to the interposer substrate, and the size of the semiconductor chip cannot be enlarged due to the restriction on the size of the bottom substrate.

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