Computer peripheral device that remains operable when central processor operations are suspended

Abstract

A peripheral device has a circuit for detecting the power management status of a central processor, a first interface for receiving data, and a second interface for coupling the peripheral device to the central processor. If the central processor is in the second power management state, the peripheral device prevents the transfer of data that would cause the central processor to change from the second power management state to the first power management state.

Description

technical field

[0001] The present invention relates generally to a method and apparatus for allowing a computer system to receive information while the CPU is asleep, and more particularly, to a peripheral device having multiple modes of operation that facilitate Or receive and buffer data while in pending state. Background technique

[0002] Power management has become increasingly important as mobile computing devices seek to extend operating time between battery charges. One way to implement power management is to completely or partially shut down computer components such as the central processing unit (CPU), hard drive, display, and other input / output (I / O) devices when the computer is not performing operations.

[0003] During some of these power management modes, also known as sleep states, the computer's CPU may stop communicating with and controlling its peripheral resources, including I / O components, and those resources may not be accessible by any other computer ...

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