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Non-volatile memory system and method for programming and reading update data

A non-volatile storage and storage system technology, applied in the field of data storage systems

Inactive Publication Date: 2009-05-06
SANDISK TECH LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, once programmed, it must be erased before the partition can be reprogrammed with new data values

Method used

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  • Non-volatile memory system and method for programming and reading update data
  • Non-volatile memory system and method for programming and reading update data
  • Non-volatile memory system and method for programming and reading update data

Examples

Experimental program
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Embodiment Construction

[0031] [Description of existing large block management technology]

[0032] FIG. 1 shows the internal architecture of a typical flash memory device. The main components include: an input / output (I / O) bus 411 and control signals 412 for interfacing to an external controller; a memory control circuit 450 for controlling internal memory through registers for command, address, and status signals operate. Also included is one or more flash EEPROM partitioned arrays 400, where each array has its own row decoder (XDEC) 401 and column decoder (YDEC) 402, a set of sense amplifiers and program control circuitry (SA / PROG) 454 and data register 404. Currently, memory segments typically include one or more conductive floating gates as storage elements, but other long-term electronic charge storage elements may be used instead. Memory cell arrays can operate with two charge levels defined for each storage element, using each element to store one bit of data. Optionally, more than two s...

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PUM

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Abstract

Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.

Description

[0001] The patent application of the present invention is a divisional application of the invention patent application filed on January 7, 2002 with the title of "Program and Read Operation of Partial Block Data in Non-Volatile Memory" and application number 02803882.7. technical field [0002] The invention relates to the field of semiconductor non-volatile data storage system architecture and its operating method, and is applied to a data storage system based on flash (flash) electrically erasable programmable read-only memory (EEPROM). Background technique [0003] A common application of flash EEPROM devices is as a mass data storage subsystem for electronic devices. These subsystems are typically implemented as removable memory cards that can be inserted into multiple host systems or as non-removable embedded memory within the host system. In both implementations, the subsystem includes one or more flash devices, and often also includes a subsystem controller. [0004]...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/02G11C16/06G11C16/02G06F12/00G11C16/10
CPCG11C16/102G06F12/0246G11C16/105G11C2216/16G06F2212/7209G06F2212/7208G06F2212/7202G06F2212/1016G06F2212/1032G06F12/02
Inventor 凯文·M·康利
Owner SANDISK TECH LLC
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