Method and device for reading misaligned data in processor
An unaligned, processor-based technology, applied in the field of data processing, can solve the problems of wasting bus bandwidth and increasing the possibility of processor pipeline hysteresis
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[0060] Figure 4 A block diagram showing a device for reading unaligned data in the processor of the present invention, which mainly includes a storage device 100, a read combined temporary register 200 (Load Combine Register, LDCR), a shift device 300 and a control device 400 . Wherein, the storage device 100 has a plurality of m-bit word groups separated by word group boundaries. In this embodiment, m is preferably 32 bits, that is, the storage device 100 is composed of a plurality of 32-bit word groups composed of. The unaligned data (ABCDEFGHIJKL) is stored in the storage device 100 and is divided into a first part 110 , a second part 120 and a third part 130 by a block boundary.
[0061] The read combination register 200 is coupled to the storage device 100 to temporarily store data read by the storage device 100 . The shifting device 300 is coupled to the read combination register 200 and the storage device 100, so as to shift the read combination register 200 and the ...
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