Semiconductor memory device having reduced voltage coupling between bit lines

Abstract

An enhanced semiconductor memory device capable of eliminating or minimizing a cell data flip phenomenon caused by capacitive voltage coupling between bit lines in different bit line pairs. Each memory cell is connected to a word line and between a pair of bit line. A first precharging and equalizing circuit us connected to a first bit line pair and a second precharging and equalizing circuit us connected to an adjacent second bit line pair. The first and second precharging and equalizing circuit are activated independently and at different times in order to reduce voltage coupling between neighboring bit lines in different bit line pairs, thereby minimizing or eliminating a cell data flip phenomenon of a neighboring memory cell caused by voltage coupling between bit lines.

Description

[0001] Cross References to Related Applications [0002] Under 35 U.S.C §119, this application claims the benefit of Korean Patent Application No. 10-2006-0008789 filed on January 27, 2006, the entire contents of which are hereby incorporated by reference. technical field [0003] The present invention relates to a semiconductor memory device, and more particularly, to a volatile semiconductor memory device such as a static random access memory (SRAM) with reduced bit line (capacitive) voltage coupling. Background technique [0004] Contemporary high-performance consumer electronic equipment, such as portable multimedia players (PMP), personal computers, and electronic communication devices (e.g., cellular phones), include large volatile memory devices such as SRAM with high-speed operation and high integration semiconductor storage device. Low power consumption and reliability during high-speed operation are especially important in semiconductor memory devices utilized in ...

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Problems solved by technology

Therefore, the potential difference formed between the selected bit line BL and the selected bit line BLb may be smaller than the sensing margin, causing the read operation of the sense amplifier to fail.

[0023] As a result, it can be seen that even though there is a constant parasitic capacitance, the reliability of the read operation is reduced because the bit line voltage coupling occurs strongly or weakly depending on the actual value of the cell data stored in the adjacent memory cells

[0024] As mentioned above, bit line voltage coupling can cause cell data flipping in write operations and read errors in read operations

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