Multiplying device
A multiplication and multiplier technology, applied in the field of multiplication devices, can solve problems such as overflow of multiplication results, and achieve the effect of reducing the scale and controlling the area of the circuit
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no. 1 Embodiment approach
[0043] Hereinafter, the case where the multiplication of the M+1-digit multiplicand A and the N+1-digit multiplier is performed (M and N are integers of 2 or more) will be described. Here, the multiplicand A and the multiplier B are signed fixed-point numbers expressed in two's complement, with a decimal point to the right of the most significant bit, and the most significant bit represents a positive or negative sign. In this fixed-point number form, the maximum positive value is 0.99...9 (the value of each bit is "011...11"), and the maximum negative value is the negative number with the largest absolute value, that is -1.00.. .0 (the value of each bit is "100...00").
[0044] Fig. 1 is a block diagram showing the structure of a multiplication device according to a first embodiment of the present invention. The multiplication device of FIG. 1 includes an encoding unit 12, an overflow detection unit 14, a partial product generation unit 16, an accumulation unit 22, and a final ad...
no. 2 Embodiment approach
[0064] FIG. 7 is a circuit diagram showing the configuration of the first partial product generating circuit 340 in the second embodiment of the present invention. The partial product generation circuit 340 of FIG. 7 includes a correction term generation circuit 346 in place of the correction term generation circuit 146 in the partial product generation circuit 140 of FIG. 2. In the second embodiment, the Booth encoding result BE_k represents the Booth encoding result other than the most significant bit.
[0065] In the second embodiment, in the multiplication device of FIG. 1, a partial product generation circuit 340 is used instead of the partial product generation circuits 140 and 180. The other constituent elements are the same as those described in the first embodiment, and therefore related descriptions are omitted.
[0066] The correction term generating circuit 346 outputs the binary number "11" as the twos complement correction term CB3 when the overflow detection result ...
no. 3 Embodiment approach
[0069] FIG. 9 is a circuit diagram showing the configuration of the first partial product generation circuit 440 in the third embodiment of the present invention. The partial product generation circuit 440 of FIG. 9 is used in the partial product generation circuit 180 of FIG. 4 so that instead of supplying the Booth coding result BE_k to the two least significant selection circuits 142, the output of the coding result correction unit 188 is provided to The selection circuit 142 which is higher than the two selection circuits 142 with the lowest order mentioned above provides the Booth coding result BE_k. In the third embodiment, the Booth encoding result BE_k represents the Booth encoding result other than the most significant bit.
[0070] In the third embodiment, in the multiplication device of FIG. 1, a partial product generation circuit 440 is used instead of the partial product generation circuits 140 and 180. The other constituent elements are the same as those described in...
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