System on a chip pipeline tester and method

Abstract

A pipeline tester is disclosed that is capable of testing systems-on-a-chip (SOCs) or Devices Under Test (DUTs) in pipeline fashion. The tester provides faster, more economical testing of such SOCs and DUTs, which are loaded sequentially into the tester. A plurality of underlying test stations are disposed in the tester. Above the test stations are disposed corresponding test fixtures which are configured to receive moveable test beds therein. The test beds are mechanically and electrically connected to the underlying test stations. Loaded within each test bed is an SOC or DUT. One or more electrical or electronic tests are performed on each SOC or DUT while the SOC or DUT is loaded in a test bed positioned above a test station. Once the test has been completed, the test bed is moved to another test station, where another electrical or electronic test is performed. Electrical or electronic tests may be performed in parallel on different DUTs or SOCs loaded into different test beds.

Description

technical field [0001] The present invention relates to the field of devices, systems and methods for testing electronic circuits by applying and measuring electrical signals, and more particularly, to assemblies, devices, systems and methods for pipeline testing of system-on-chip (SOC) or other integrated circuits method. Background technique [0002] To ensure proper functionality and reliability, manufacturers typically test SOC integrated circuits (ICs) before shipping them to consumers. A system commonly used to test SOC ICs is the Agilent 93000 SOC tester that supports concurrent testing. Portions of the Agilent 93000 SOC Tester are described in U.S. Patent Nos. 6,756,778 to Hirschmann, entitled "Measuring and / or calibrating a Test Head," to Botka et al. Patent No. 5,558,541, and US Patent No. 5,552,701, entitled "Docking System for an Electronic Circuit Tester," to Veteran et al. [0003] As shown in Figures 1 and 2, the Agilent 93000 tester 100 includes a test hea...

AI Technical Summary

Problems solved by technology

There are several disadvantages of the concurrent testing method: not all tests can be run concurrently; concurrent testing requires a larger upfront investment in equipment in order to design a DUT suitable for concurrent testing; many chip schematics are generally not suitable for "use Design for Concurrent Test"; and "Design for Concurrent Test" can result in a sub-optimal chip design

[0026] In summary, a review of current test options shows that: parallel test methods can test DUTs at rates up to about 4 times that of traditional methods, but require very complex systems; strip test methods only reduce handler indexing time; Hides design costs and other tradeoffs

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