External memory controller timing configuration device and method

Abstract

The invention relates to the chip field, providing an external memory controller timing configuration device and method, where the device comprises configuration register interface module and timing control module, where the configuration register interface module is used to configure and generate control signal's advanced invalid parameter and control parameter, and chip select signal according to the current memory parameter; the timing control module is used to generate control signal by the chip select signal according to the received control signal's advanced invalid parameter and control parameter; the control signal comprises write enable signal and/or output enable signal. And it can solve the problem of influencing the control on the current memory caused by stable write enable signal or output enable signal, or generation delay of control signal.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a device and method for timing configuration of an external memory controller. Background technique [0002] As a general storage interface, the external memory controller is suitable for controlling the read and write operations of various storage devices similar to the asynchronous memory (memory) interface. [0003] When controlling its read and write operations, the commonly used control signals include an output enable signal (OEN), a write enable signal (WEN) and a chip select signal (CS). The generation of OEN or WEN provided in the prior art Most of the control parameters are write enable delay parameters or output enable delay parameters. Among them, the write enable delay parameter is the time delay between the valid time start of the write enable signal and the effective time of CS, and the output enable delay parameter is the output enable signal The effective ti...

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Problems solved by technology

[0010] The embodiment of the present invention provides a device and method for timing configuration of an external memory controller, which solves the problem in the prior art that the effective control of the write enable signal or the output enable signal is not comprehensive, resulting in the operation of the external memory The timing does not meet the timing requirements, and the timing configuration is not flexible enough, and there is a single defect in the control of the write enable signal or output enable signal

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