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Memory module

A memory module and feedback loop technology, applied in the field of memory modules, can solve problems such as large skew and distortion of output data, and the problem that the output detection window cannot be determined, and achieve the effect of enhanced reliability

Inactive Publication Date: 2007-09-05
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Also, depending on how the DIMMs are used (number of slots used, mix of DIMMs with different capacitances, etc.), there may be a large skew in the output data, causing the problem that the output detection window cannot be determined

Method used

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Experimental program
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Embodiment Construction

[0028] Before describing the embodiments of the present invention, a description will be given of how timing adjustment of a clock signal is performed at the time of memory module development. Figure 1 shows the general construction of a DIMM. The DIMM 10 shown here includes a plurality of SDRAM devices 16, and a PLL-based clock driver 20 for distributing clock signals to the SDRAM devices.

[0029] In DIMM 10 , differential clock signals CLK, / CLK input via DIMM edge terminals are phase adjusted by PLL-based clock driver 20 before being distributed to individual SDRAM devices 16 . Here, / CLK is an alternative symbol for CLK with a horizontal line across it. Each SDRAM device 16 operates in synchronization with the supplied clock signal, and outputs differential data DQS, / DQS to the DIMM edge terminal. In the DIMM 10, reference numeral 12 designates a CLK terminal (or / CLK terminal), and 14 designates a DQS terminal (or / DQS terminal). The wiring pattern for the clock sign...

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Abstract

The present invention provides a storage module, which has a memory array mounted on it and works synchronously with the clock signal; wherein, rules are set down to ensure the clock phase can be tuned accurately according to the service condition of the storage module. The storage module with a memory array working synchronously with clock signal comprises: a phase lock loop circuit, which is designed to produce clock signal output, wherein, the clock signal output is adjusted so that the phase of the feedback signal matches the phase of the clock signal input, and the feedback signal is obtained by forcing the clock signal output to pass through a feedback loop; and, a switching unit, which is designed to change the load in the feedback loop selectively according to the external signal.

Description

technical field [0001] The present invention relates to a memory module having an array of memory devices mounted thereon and operating in synchronization with a clock signal. Background technique [0002] Currently, Synchronous Dynamic Random Access Memory (SDRAM) is the main type of memory used as the main memory of personal computers and the like. By operating synchronously with the system bus clock, SDRAM has the characteristic of achieving a higher access speed, and is often used in the form of a dual in-line memory module (DIMM). A DIMM is a memory module with separate independent contacts on both sides, the total number of pins on both sides is eg 184, and it is capable of transferring data in blocks of 72 bits. [0003] In the DIMM, clock distribution is performed by using a PLL (Phase Locked Loop) circuit mounted on the DIMM; that is, the PLL circuit adjusts the phase of a clock signal input via the terminal of the DIMM and distributes the phase-adjusted clock sign...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/22G11C11/4076
CPCG11C29/022G11C7/222G11C29/50008G11C5/04G11C29/50012G11C29/028G11C29/02G11C7/22G11C11/4076H03L7/0812G11C2207/2254
Inventor 中野力藏
Owner FUJITSU LTD