Wafer container with secondary wafer restraint system

Abstract

A wafer container providing improved wafer restraint during physical shock events. In embodiments of the invention, a secondary wafer restraint structure defining a plurality of notches is interposed between opposing wafer restraint members on the door of the container. The notches may be defined by one or more converging edges or surfaces meeting at a junction. The junctions are positioned so as to align with the wafer receiving portions of each opposing pair of wafer restraint member so that when the door is fully sealingly engaged with the enclosure of the container, the edge of the wafer is contacting the junction. In this position, any vertical movement of the wafer due to shock imparted to the container causes the wafer to contact the converging surfaces or edges, thereby limiting such movement. The positioning of the secondary wafer restraint structure between and proximate opposing fingers of the primary wafer restraint limits deflection of the wafer between support points and thereby further inhibits the wafer from ''jumping'' out of the supports and cross-slotting.

Description

[0001] Related applications [0002] This application claims rights based on U.S. Provisional Patent Application No. 60 / 630,546, filed November 23, 2004, and entitled "Wafer Container With Auxiliary Wafer Confinement System ( WAFER CONTAINER WITH SECONDARY WAFERRESTRAINT SYSTEM), which is hereby incorporated by reference in its entirety. technical field [0003] The present invention relates generally to sealable containers for semiconductor wafers, and more particularly to wafer containment systems for wafer containers. Background technique [0004] Converting semiconductor wafers into integrated circuit chips often involves many steps in which the wafers are repeatedly handled, stored and shipped. Wafers must be transported between workstations and between fabs. Wafers are fragile and easily damaged by physical shock. Additionally, electrostatic charge buildup and discharge near semiconductor wafers can cause severe damage. Due to the damage-prone nature and high value...

AI Technical Summary

Problems solved by technology

However, prior art wafer confinement structures are not very satisfactory in some situations

In some cases, the wafer confinement structure may allow the wafer to translate too far vertically during a physical shock event, cau

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