Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements

Abstract

Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them.

Description

technical field [0001] The invention specifically relates to a class of non-volatile flash memory EEPROM (Electrically Erasable and Programmable Read-Only Memory) cell arrays using dielectric material charge storage elements. Background technique [0002] There are many commercially successful nonvolatile memory products that have conductive floating gates in their memory cells, usually doped polycrystalline materials, on which a charge is stored to store a level of data state . The usual form of such a memory cell has a "split channel" between the source and drain diffusion regions. The floating gate of the cell is on top of one part of the channel, and the word line (also known as the control gate) is on the other part of the channel, just like the floating gate. This effectively creates a cell with two transistors in series, one transistor (the memory transistor) with a combination of the amount of charge on the floating gate and the voltage on the word line that contro...

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Problems solved by technology

But since there is a limit to how much a given circuit arrangement can be scaled down by simple scaling, redesigning the cell has the immediate effect of making one or more features occupy less area

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