Quick self-adapted noise elimination module based on FPGA design
An adaptive and denoising technology, applied in the direction of adaptive network, impedance network, digital technology network, etc., can solve the problems of filter performance degradation, no consideration of LMS filter versatility, no adaptive noise canceller, etc., to achieve The effect of improving performance
Inactive Publication Date: 2010-11-03
INST OF BIOMEDICAL ENG CHINESE ACAD OF MEDICAL SCI
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Problems solved by technology
At present, some researchers have begun to use FPGA chips to develop LMS digital filter products, but the existing technologies mainly focus on how to reduce the occupation of FPGA chip resources within a certain error range, without considering the universality of LMS filters
In this way, different types of signal processing must be operated by personnel with professional knowledge and use cumbersome algorithms to calculate the appropriate filter parameters. Since the signal is susceptible to noise interference, its preset filter parameters are not necessarily all suitable, even for the processing of signals of the same class
This method of setting parameters in advance cannot make real-time adjustments to some noise and interference signals, resulting in a decrease in filter performance.
In particular, this method is more difficult to detect the desired signal from a very weak signal, and there is no adaptive noise canceller based on FPGA design
Method used
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[0027] Embodiments of the present invention are described in further detail below in conjunction with the accompanying drawings:
[0028] A fast adaptive noise reduction module based on FPGA design, the FPGA used is the Spartan XC3S400 chip of Xilinx Company, all registers, all decimal multipliers, all decimal adders, all dividers, inverters and All integer multipliers are IP cores designed by Xilinx for their own company's FPGA. The decimal multipliers and integer multipliers are modified on the basis of the IP cores of Xilinx's 16-bit integer multipliers. The decimal multipliers are Take the high sixteen bits of the 32-bit output of Xilinx's 16-bit integer multiplier as the output of the decimal multiplier, and the integer multiplier takes the low sixteen bits of the 32-bit output of Xilinx's 16-bit integer multiplier as Output of the fractional multiplier. The numbers stored in all the above-mentioned registers and inverters are fixed-point numbers, and the numbers operate...
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This invention relates to a quick adaptive noise-eliminating module based on FPGA design connected by a signal conversion circuit, a mum value computation circuit, a LMS filter circuit and an output regulation circuit, in which, original signal s(n) and noise input r(n) are connected to two input ends of the signal conversion circuit, input signals1(n) output by the conversion circuit and reference signal r1(n) are connected to two input ends of the LMS filter, the reference signal is also connected with the input of the mum value computation circuit and the mum value output by the computation circuit is connected to the third input end of the LMS filter, and the output signal y(n)of which is connected with regulation signal m to the output regulation circuit and the output of which outputs signal Y(n) without noises, which applies a LMS to compute filter parameters automatically acording to characters of input signals and regulats the parameters to eliminate noises so as to increase performance of routine LMS.
Description
technical field [0001] The invention relates to the field of digital filter equipment, in particular to a fast self-adaptive denoising module designed based on FPGA. Background technique [0002] Field Programmable Gate Array (FPGA, Field Programmable Gate Array in English) emerged as a semi-custom circuit of an application-specific integrated circuit (ASIC). Due to the limited number of circuits, Field Programmable Gate Array (FPGA) chips are widely used. At present, some researchers have begun to use FPGA chips to develop LMS digital filter products, but the existing technologies mainly focus on how to reduce the occupation of FPGA chip resources within a certain error range, without considering the generality of LMS filters. In this way, different types of signal processing must be operated by personnel with professional knowledge and use cumbersome algorithms to calculate the appropriate filter parameters. Since the signal is susceptible to noise interference, its prese...
Claims
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IPC IPC(8): H03H21/00H03H17/02
Inventor 胡勇沈冲飞
Owner INST OF BIOMEDICAL ENG CHINESE ACAD OF MEDICAL SCI