Serial self-adapting noise elimination module based on FPGA design
An adaptive and noise-removing technology, which is applied in the direction of adaptive network, logic circuit using basic logic circuit components, logic circuit using specific components, etc., can solve the problem of LMS filter development cost and product cost increase, and it is not suitable for medium and low speed Signal processing, multi-logic resources and other issues to achieve the effect of reducing development costs, improving performance and reducing costs
Inactive Publication Date: 2011-06-08
INST OF BIOMEDICAL ENG CHINESE ACAD OF MEDICAL SCI
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Problems solved by technology
At present, the use of FPGA chips to develop LMS (least mean square algorithm) digital filter products is more and more widely used. The existing technology is mainly aimed at processing high-speed digital signals, and it is realized by using a parallel multi-stage pipeline structure. The existing problems are : The parallel multi-stage pipeline structure needs to consume more logic resources, and needs to use high-performance FPGA chips for processing, especially when the order of the LMS filter is relatively high, resulting in a significant increase in the development cost and product cost of the LMS filter , not suitable for the processing of medium and low speed signals when the order of the LMS filter is relatively high
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[0036] Embodiments of the present invention are described in further detail below in conjunction with the accompanying drawings:
[0037] The FPGA (Field Programmable Gate Array) chip used in the FPGA-based serial self-adaptive denoising module is the Spartan XC3S400 chip of Xilinx Company, all registers, all decimal multipliers, all decimal adders, and all dividers in the following description , all registers, all integer multipliers and multiplication accumulators, inverters and counters are the IP cores of Xilinx's FPGA chip, where the decimal multiplier and integer multiplier are in the 16-bit integer multiplier of Xilinx Modified on the basis of the IP core, the decimal multiplier takes the high sixteen bits of the 32-bit output of Xilinx's 16-bit integer multiplier as the output of the decimal multiplier, and the integer multiplier takes Xilinx's 16-bit integer The lower sixteen bits of the 32-bit output of the multiplier are used as the output of the fractional multipli...
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The invention relates to a serial self-adaptive noise cancellation module designed based on an FPGA in the digital filtering equipment field. The two input terminals of a signal conversion circuit of the module are respectively connected with an original signal s(n) and a noise input signal r(n), an input signal s1(n) and a reference signal r1(n) outputted by the signal conversion circuit are respectively connected to two input terminals of a serial LMS filter circuit, a minification b and a conditioning signal m outputted by the signal conversion circuit are respectively connected with the input terminal of a Mu value calculating circuit and the input terminal of an output conditioning circuit, a Mu value outputted by the Mu value calculating circuit is connected with the third input terminal of the serial LMS filter circuit, an output signal y(n) of the serial LMS filter circuit is connected with the other input terminal of the output conditioning circuit, and the output conditioning circuit outputs a noise cancellation signal Y(n). The noise cancellation module can rapidly and automatically adjust the parameters to eliminate noise by adopting the serial LMS filter circuit, which improves the performance of the LMS filter, reduces the costs of the LMS filter, and can be widely used in signal de-noising applications.
Description
technical field [0001] The invention belongs to the field of digital filter equipment, in particular to a serial self-adaptive denoising module designed based on FPGA. Background technique [0002] Field Programmable Gate Array (FPGA, Field Programmable Gate Array in English) emerged as a semi-custom circuit of an application-specific integrated circuit (ASIC). Due to the limited number of circuits, Field Programmable Gate Array (FPGA) chips are widely used. At present, the use of FPGA chips to develop LMS (least mean square algorithm) digital filter products is more and more widely used. The existing technology is mainly aimed at processing high-speed digital signals, and it is realized by using a parallel multi-stage pipeline structure. The existing problems are : The parallel multi-stage pipeline structure needs to consume more logic resources, and needs to use high-performance FPGA chips for processing, especially when the order of the LMS filter is relatively high, res...
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IPC IPC(8): H03H21/00H03H17/02H03K19/173
Inventor 胡勇沈冲飞崔红岩谢小波
Owner INST OF BIOMEDICAL ENG CHINESE ACAD OF MEDICAL SCI