Semiconductor storage apparatus and semiconductor integrated circuit incorporating the same

Abstract

A semiconductor storage apparatus wherein the number of memory cells used as bypass capacitors can be dynamically changed. In each memory block, a selector signal line is provided in parallel with each word line. In a pair of word line and selector signal line adjacent to each other, the states thereof are maintained such that they are opposite to each other. Additionally, in each memory block, abranch of a power supply line is provided in parallel with each bit line. In each memory cell, a first transistor connects a capacitor to the bit line in accordance with the state of the word line, while a second transistor connects the same capacitor to the power supply line branch in accordance with the state of the selector signal line. In the memory cells aligned in the row direction, the gatesof the first transistors are connected to the same word line, while the gates of the second transistors are connected to the same selector signal line.

Description

technical field [0001] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device mounted on a semiconductor integrated circuit. Background technique [0002] A dynamic semiconductor memory device (DRAM) is easy to be highly integrated and large in capacity. In recent years, DRAM (hybrid DRAM), which is integrated with logic circuits on the same chip, has been widely used. Since the data transmission speed of the hybrid DRAM is particularly high, it is suitable for a system LSI (such as a graphics LSI) that performs high-speed calculation and communication of a large amount of data. On the other hand, compared with ordinary DRAM, the manufacturing process of hybrid DRAM is complicated. As a conventional technique for simplifying the manufacturing process of a hybrid DRAM, for example, the following techniques are known (for example, refer to Patent Document 1). In the DRAM employing this prior art, a part of the ...

AI Technical Summary

Problems solved by technology

[0004] In the aforementioned DRAM of the prior art, the potentials of the bit lines and the word lines connected to the memory cells used as bypass capacitors are fixed, so these memory cells completely lose their original storage function (storing bit information). ability)

Images