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Layout modification to eliminate line bending caused by line material shrinkage

A technology of bending and supporting features, applied in the photoengraving process, instruments, electrical components, etc. of the pattern surface, which can solve the problems of corrosion, device failure, damage, etc.

Inactive Publication Date: 2008-06-18
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Wire bending can lead to damage and / or corrosion of silicon ("polysilicon") wires and eventually cause device failure and loss

Method used

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  • Layout modification to eliminate line bending caused by line material shrinkage
  • Layout modification to eliminate line bending caused by line material shrinkage

Examples

Experimental program
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Embodiment Construction

[0016] As used herein, the term "mask" should be broadly understood to refer to a general patterning device (including, but not limited to, photoresist) that can be used to impart a patterned cross-section to an incoming beam of light, the The patterned cross-section corresponds to a target pattern to be formed in the target portion of the substrate. As used herein and unless specified otherwise, the term "feature" refers to a pattern defined by a mask. For example, gate structures may be defined in a mask image by gate features. As used herein and unless otherwise specified, the term "structure" refers to a pattern formed in a layer underlying a patterned mask. For example, the gate structure may be a gate formed by etching a layer (eg, polysilicon layer) underlying the patterned resist.

[0017] 2A-3 depict exemplary mask images including support features, semiconductor structures including support structures, and methods for fabricating the exemplary features and structur...

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Abstract

A semiconductor device and a method for fabricating a semiconductor device with reduced line bending is provided. The method can include forming a first layer and depositing a photoresist layer on the first layer. The photoresist layer can be patterned, such that the patterning comprises at least one support feature (271) disposed adjacent to an outside of a corner feature (250).

Description

technical field [0001] The present invention relates to etching processes during the manufacture of semiconductor devices. More particularly, the present invention relates to methods for reducing the effects of etch-related photoresist shrinkage during semiconductor device fabrication. Background technique [0002] For example, lithographic projection equipment (tools) may be used in the fabrication of integrated circuits (ICs). When using various tools, a mask can be used that contains a circuit pattern corresponding to the various layers of the IC, and this pattern can be imaged onto a target portion on a substrate (e.g., silicon or other wafer including semiconductors) (eg, including one or more dies), wherein the substrate has been coated with a layer of radiation-sensitive material (eg, photoresist). The photoresist is selectively exposed to radiation (eg, ultraviolet light), and then developed to form a patterned resist. The patterned resist should ideally be respon...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/461H01L21/302
CPCH01L21/0273G03F7/70425
Inventor 弗拉迪米尔·阿莱克谢耶维奇·乌克兰采夫马克·E·梅森詹姆斯·沃尔特·布拉奇福德布赖恩·阿什利·史密斯布赖恩·爱德华·霍尔农德克·诺埃尔·安德森
Owner TEXAS INSTR INC