Semiconductor package substrate increasing static dissipation capability

Abstract

The invention relates to a semiconductor package substrate capable of reinforcing static dissipating ability, comprising a dielectric layer, a plurality of pins, a plurality of first static guide circuits, a plurality of second guide circuits and a solder mask. The first static guide circuits and the second static circuits are formed in a plurality of static dissipating areas of the dielectric layer, the static dissipating areas are in electric insulating neighbored arrangement and are exposed out of the solder mast, further the first static guide circuits are connected with a part of pins, thereby reinforcing the static dissipating ability of the substrate in manufacture procedure.

Description

technical field [0001] The invention relates to a semiconductor packaging substrate, in particular to a semiconductor packaging substrate with enhanced electrostatic dissipation capability. Background technique [0002] Objects or human bodies will accumulate static electricity due to friction during the moving process. The electrostatic voltage is quite high, up to thousands of volts or even tens of thousands of volts. When it is discharged instantaneously, it will seriously damage the surrounding electronic components, that is, "electric discharge". In the process of semiconductor packaging, the problem of electrostatic discharge damage to integrated circuit chips will also be encountered. [0003] Such as figure 1 As shown, a conventional semiconductor package substrate 100 mainly includes a dielectric layer 110 , a plurality of pins 120 and a solder resist layer (not shown). A plurality of packaging units 111 are defined on the dielectric layer 110 . The pins 120 are ...

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