Active part array base board and its making method
An array substrate and active element technology, which is applied in the field of manufacturing thin film transistor array substrates, can solve problems such as high difficulty, reduced element performance, and increased cost.
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Embodiment approach 1
[0076] [step one]
[0077] Referring to FIG. 1 and FIGS. 2A to 2C , firstly, a patterned first metal layer 223 is formed on the substrate 221 . According to the present invention, the substrate 221 can be, for example, a glass substrate or a plastic substrate, and the patterned first metal layer 223 can be a single metal layer or a multiple metal layer; in this embodiment, the patterned first metal layer 223 is composed of an upper The metal layer 223a and the lower metal layer 223b are formed. The material of the upper metal layer 223a can be, for example, aluminum, and the material of the lower metal layer 223b can be, for example, titanium, molybdenum, or an alloy thereof.
[0078] A first metal layer (not shown) is first deposited by a chemical vapor deposition method, and then a first photomask process is performed using, for example, a binary photomask, so as to be placed on a predetermined position above the substrate 221, A patterned first metal layer 223 is formed as...
Embodiment approach 2
[0099] [step one]
[0100] Referring to FIGS. 9 and 10A to 10C, a first photomask process is performed on the substrate 321 to form a patterned first metal layer 323 as shown in FIG. 9 at a predetermined position above it. The method and materials are the same as the first step above, that is, depositing a first metal layer (not shown), and then performing a first photomask process to form a patterned first metal layer on a predetermined position of the substrate 321 .
[0101] In this manner, the patterned first metal layer 323 is a multi-metal layer, but not limited thereto, and is composed of an upper metal layer 323a and a lower metal layer 323b. As shown in FIG. 9 , the patterned first metal layer 323 of this mode also includes a plurality of gate wires 123 , a plurality of gates 122 connected to these gate wires 123 and a plurality of gate connection pads 121 , the cross-sectional views are shown in Figures 10A to 10C.
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