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Clocktree tuning shims and shim tuning method

A clock and cell library technology, applied in electrical components, instruments, program control design, etc., can solve the problems of chip performance degradation, increased clock distribution network time, and large time consumption.

Inactive Publication Date: 2008-12-10
ALTERA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Similarly, this stage also consumes a lot of time
[0008] As circuits have become larger and more complex, the time required to design clock distribution networks has increased significantly
Indeed, the clock tree tracking and error process described above can add a month or more to said project, and even the end result is sometimes still sub-optimal, necessitating a degradation in chip performance

Method used

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  • Clocktree tuning shims and shim tuning method
  • Clocktree tuning shims and shim tuning method
  • Clocktree tuning shims and shim tuning method

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Embodiment Construction

[0021] One concept upon which many of the embodiments described or illustrated herein are libraries of custom pad cells used by clock tree synthesis tools to design and place clock distribution networks. Each custom pad cell in the library is for or represents a model of a corresponding structure in the circuit, and the structure is an active delay element that introduces a different corresponding delay into the clock signal. Each padding cell is named in units corresponding to the delay introduced by the physical embodiment it represents (ie, the particular active delay element). The available latencies across the library span a range large enough to handle the range of clock skew a designer may encounter during the design process. Furthermore, the full set of available delays is grouped into levels fine enough to provide the degree of fine-tuning required by the designer during the design process. Thus, by replacing one padding cell with another in the clock distribution ne...

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Abstract

A digital storage medium storing electronic data for use with a clock tree design tool to design a clock distribution network within an integrated circuit, the electronic data implementing a library of shim cells, wherein each of the shim cells in the library represents a physical embodiment of a different clock driver cell of a plurality of clock driver cells and wherein all of the shim cells in the library are interchangeable in the clock distribution network design without requiring any change in placement or routing within the integrated circuit to maintain compliance with design requirements for the integrated circuit.

Description

[0001] This application asserts the benefit of US Provisional Patent Application No. 60 / 450,076, filed February 25, 2003, and US Provisional Patent Application No. 60 / 465,089, filed April 24, 2003. technical field [0002] The present invention relates to clock tree tuning methods and tools such as may be used in integrated circuit design. Background technique [0003] in such as figure 1 In the shown physical embodiment of the digital circuit on chip 10, it is necessary to provide a network 12 for clocking components (such as registers, flip-flops, latches and other logic devices) or The clocked component group 14 distributes copies of the clock signal. Networks that perform this function are called clock distribution nets or clock trees. It is called a tree because of the hierarchical nature of its structure with multiple layers of branches. [0004] In large-scale circuits with many components, clock tree design can be a very challenging part of the overall circuit des...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50G06F9/45H01LH01L21/00
CPCG06F30/30
Inventor 詹姆斯·E·曼德里
Owner ALTERA CORP