Bus arbitration unit for guaranteeing access sequence and its implementing method

A technology of bus arbitration and sequencing, which is applied in the direction of instrumentation, electrical digital data processing, etc., can solve the problem of processor 2 reading wrong data, etc., and achieve the effect of satisfying the correctness

Inactive Publication Date: 2009-01-14
WUXI ZGMICRO ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
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Then, processor 2

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  • Bus arbitration unit for guaranteeing access sequence and its implementing method
  • Bus arbitration unit for guaranteeing access sequence and its implementing method
  • Bus arbitration unit for guaranteeing access sequence and its implementing method

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Embodiment Construction

[0027] The present invention designs such a bus arbitration unit: when the bus arbitration unit is idle, if there are multiple requests at the same time, the application result is generated according to a certain priority arbitration strategy, and other unresponsive requests are suspended and saved down. When the bus arbitration unit is busy, subsequent requests will be suspended directly, and all requests coming in this cycle can only be processed after all requests before this time are processed. In short, this bus arbitration unit can ensure the first-come-first-response requests of multiple modules, and then consider the priority of each module itself, ensuring that the sequence of accessing memory by multiple modules is not disrupted, satisfying multiple Correctness of modules working together.

[0028] figure 1 is a block diagram of the bus president unit according to the present invention.

[0029] Such as figure 1 As shown, the bus president unit according to the p...

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Abstract

The invention relates to a bus arbitration unit which ensures access precedence, and a realization method thereof. The bus arbitration unit comprises a queue memory which is used for storing request packets sent at different time, a bit mask unit which is used for masking the earliest request packet so as to mask off the request which is responded, and an arbitration unit which is used for arbitrating the masked request packet so as to select one of the requests for response. By ensuring that the request arriving first and sent by a plurality of modules at different time is first responded, the unit and the method of the invention arbitrate according to the precedence of a plurality of requests arriving simultaneously, thereby ensuring that the precedence of multiple modules for accessing the memory is not disorganized and meeting the correctness of the team work of a plurality of modules.

Description

technical field [0001] The invention relates to a bus arbitration unit which guarantees access sequence and its realization method. Background technique [0002] In a system-on-chip (SoC), there are multiple functional modules that need to access memory, such as multiple processors, DMA, and hardware accelerator modules on-chip. System memory resources include off-chip memory, such as SDRAM, DDR, NOR. At the same time, in order to reduce the access delay, there may also be an on-chip shared memory, such as SRAM. [0003] In the SoC system, the processor and other functional modules operate independently and cooperate with each other to access various memory resources as needed. Therefore, each memory resource may be accessed and requested by multiple functional modules at the same time. However, according to the physical characteristics of the memory, a large-capacity memory generally only allows one read and write access at the same time. Therefore, the access of multip...

Claims

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Application Information

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IPC IPC(8): G06F13/16G06F13/18
Inventor 林川
Owner WUXI ZGMICRO ELECTRONICS CO LTD
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