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Test structure and monitoring method for CUI effect of shallow plough groove isolation technology

A technology of test structure and isolation structure, applied in semiconductor/solid-state device test/measurement, electrical components, electrical solid-state devices, etc., can solve problems such as easy breakdown, and achieve the effect of avoiding breakdown and improving reliability.

Active Publication Date: 2012-01-18
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This layer of material cannot be effectively removed in the subsequent process, resulting in the final growth of the gate oxide layer (gate oxide), the gate oxide layer will be thinner in the STI corner area, making it easier to break down

Method used

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  • Test structure and monitoring method for CUI effect of shallow plough groove isolation technology
  • Test structure and monitoring method for CUI effect of shallow plough groove isolation technology

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Experimental program
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Embodiment Construction

[0012] A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0013] Such as figure 1 As shown, the test structure of the present invention includes the active region 1 of the lower layer and the polysilicon 2 of the upper layer, and one side of the active region 1 and the polysilicon 2 is respectively provided with a through hole 3, and a metal line (not shown) is drawn out in the through hole 3 As shown in the figure), the active region 1 adopts a curved structure (for example, a shape similar to a square wave as shown in the figure), so as to generate a plurality of shallow trench isolation corners 10 . Wherein, the width of the active region 1 adopts the minimum design rule.

[0014] The method of using the test structure of the present invention to monitor whether the Cooy effect occurs in the shallow trench isolation process is to monitor the breakdown between the active region 1 and the polysilic...

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Abstract

The invention provides a testing structure and a monitoring method used for Cui effect in a shallow channel separation process. The testing structure comprises an active area and a multi-crystal silicon which is formed on the upper layer of the active area; the active area and the multi-crystal silicon are respectively provided with a through hole so as to lead out metal wires; and the active area adopts a bent structure so as to generate a plurality of shallow channel separation turning angles. The monitoring method judges whether Cui effect is generated at the shallow channel separation turning angle by monitoring the breakage voltage between the active area and the multi-crystal silicon at the shallow channel separation turning angle of the active area. By adopting the testing structure and the monitoring method of the invention, whether Cui effect is generated at the shallow channel separation turning angle can be conveniently judged so as to take corresponding measures to avoid the breakage of a grid oxidation layer, thus improving the reliability of the whole semiconductor process further.

Description

technical field [0001] The invention relates to a semiconductor test process, in particular to a structure and a method for monitoring the Kuy effect in a shallow trench isolation process. Background technique [0002] In the prior art, shallow trench isolation (Shallow Trench Isolate, STI) technology has been widely used in the isolation process. Before doing STI etching, a layer of thermal oxide (thermal oxide) is grown on the silicon substrate, and then a layer of silicon nitride is deposited as a stop layer for STI chemical mechanical polishing (CMP). After STI etching, in order to eliminate the damage caused by etching, reduce the damage of subsequent STI chloride (HDP) deposition, and release its stress, a thermal oxide layer will be formed at high temperature. Under this high-temperature process, in the STI corner area, nitrogen will pass through the underlying thermal oxide layer to reach the silicon bottom layer, forming a layer of hard-to-remove substances (for ex...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/544H01L21/66
Inventor 肖海波
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP