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Semiconductor device manufacturing method using double patterning and mask

A manufacturing method and double-patterning technology, applied in the field of mask manufacturing, can solve the problems of not considering the yield, improvement, and decline of yield

Inactive Publication Date: 2009-03-04
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Conventional technology is good at eliminating layout patterns that are fatal to manufacturing, but there are cases where the yield decreases due to distribution of layout patterns that should not be distributed.
In addition, no consideration is given to improving the yield of each process after distribution according to the method of distribution

Method used

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  • Semiconductor device manufacturing method using double patterning and mask
  • Semiconductor device manufacturing method using double patterning and mask
  • Semiconductor device manufacturing method using double patterning and mask

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

figure 1 The manufacturing method of the manufacturing apparatus using the semiconductor device formed by double patterning is shown. like figure 1 As shown, in the LSI manufacturing flow of the present embodiment, first, the intended design layout ( LFS1 ) is determined. In the next step (LFS2), the design layout is divided / distributed, RET (Resolution Enhancement Technique), OPC (Optical Proximity Correction), and PRC (Process RuleCheck) inspection) and MDP processing (Mask Data Preparation: mask data processing) and the like. Thus, layout pattern data 1, 2, . . . N (LFS3 to 5) are obtained. In addition, the correction of optical proximity effect here means not only correction of optical proximity effect, but also correction of pattern distortion in manufacturing in a broad sense. In addition, the PRC refers to lithography verification to detect problems in the photolithography process, MRC (Mask Rule Check) to detect problems in the mask process, inspection of conditions...

Embodiment 2

In this embodiment, it means Figure 4 Another example of assigning the design layout pattern to a plurality of masks performed in the shown division / assignment condition determination step (SDS8). Different from the case where the originally separated design layout pattern is allocated to the plurality of masks shown in Example 1, the originally unseparated design layout pattern is divided into a plurality of layout patterns, and then allocated to a plurality of Example on the mask. Also, an example is shown in which allocation of masks for allocated layout patterns is differentiated. exist Figure 9A In, the layout pattern group LPG2 which is a design layout pattern is shown. in addition, Figure 9B and Figure 9C It is a schematic diagram showing an example of dividing the layout pattern group LPG2 at the same location as the layout patterns LP11 and LP12.

[0041]

exist Figure 9B , among the divided layout patterns LP11 and 12, the layout pattern LP11 having a rel...

Embodiment 3

This example gives: Figure 4 In the shown division / distribution condition determination step (SDS8), an example in which an auxiliary pattern is formed on the mask in addition to the layout pattern. The so-called auxiliary pattern is a pattern added to the original design layout pattern in order to set an ideal pattern pitch or pattern density in manufacturing. By adding the auxiliary pattern, the effect of improving the resolution and expanding the depth of focus can be obtained, and the shape of the pattern can be improved.

[0045]

Figure 10A The layout pattern LP21 which is a design layout pattern is shown. Figure 10B means with Figure 10A The layout pattern LP21 corresponding to the pattern AP21 actually obtained on the wafer.

[0046]

Figure 10C is true Figure 10A Example after adding auxiliary pattern SP22. The auxiliary pattern is roughly divided into: only obtained on the wafer Figure 10B A non-resolution auxiliary pattern of a pattern like AP21; and...

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Abstract

To provide a semiconductor device manufacturing method using double patterning, in which layout patterns are distributed avoiding yield reduction factors. The semiconductor device manufacturing method includes the steps of: preparing a plurality of masks for use in the double patterning; and performing the double patterning using the plurality of masks. The step of preparing the plurality of masks includes a step of distributing a group of layout patterns to the plurality of masks, in accordance with characteristics of exposure steps respectively using the plurality of masks, and in consideration of size of the layout patterns.

Description

technical field [0001] The present invention relates to a method for manufacturing a semiconductor device and a mask, and more particularly, to a method for manufacturing a semiconductor device having a fine semiconductor circuit pattern, and a mask for manufacturing. Background technique [0002] As a strong complement to the lithography process at the 32nm node, dual patterning is proposed. The so-called double patterning is a process of distributing a layout pattern on a plurality of masks and performing multiple exposures, etching, and the like to obtain a designed layout pattern. When the distance between the two layout patterns is small, if the two layout patterns are formed on the same mask, the two layout patterns cannot be separated and formed on the wafer. To avoid such a problem, double patterning is used. [0003] The layout pattern assignment process is performed as follows, for example. That is, based on the layout pattern to be processed and the extra...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/00H01L21/027G03F1/14G03F1/36G03F1/68G03F1/70
CPCG03F1/144G03F7/70466G03F7/70283G03F1/70G03F1/36G03F7/70441
Inventor 田冈弘展茂庭明美坂井淳二郎
Owner RENESAS ELECTRONICS CORP