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Test system

A test system and a technology to be tested are applied in the direction of digital circuit test, electronic circuit test, and electrical measurement, which can solve problems such as consuming a lot of time and achieve the effect of improving efficiency

Inactive Publication Date: 2009-05-20
PRINCETON TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] When using the above two methods for chip testing, when the number of chips to be tested is quite large, it will take a considerable amount of time to complete the test

Method used

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Embodiment Construction

[0028] Please refer to FIG. 3 . FIG. 3 is a schematic diagram of the test system proposed by the present invention. As shown in FIG. 3 , a test system 30 of this embodiment is used to test a plurality of DUTs 321 - 323 . The test system 30 includes a test host 34 and a plurality of processors 362 - 363 . The test host 34 is used to provide multiple control signals, and according to multiple measurement results T generated by the multiple DUTs 321-323 R1 ~T R3 , to determine the test results of the plurality of DUTs 321 - 323 . A plurality of processors 362-363 are coupled to the test host 34 for generating a plurality of test signals S according to the plurality of control signals T2 ~S T3 . Wherein the plurality of DUTs 322-323 are based on the plurality of test signals S T2 ~S T3 , respectively generate the multiple measurement results T R2 ~T R3 . In a specific embodiment, the test host 34 is a logic tester, and the DUTs 321 - 323 are respectively an integrated ci...

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PUM

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Abstract

The invention discloses a test system for testing a plurality of elements to be tested. The test system comprises a test main machine and a plurality of processors, wherein the test main machine is used to provide a plurality of control signals, and determine the test results of the plurality of the elements to be tested according to a plurality of test results generated by the elements to be tested; the plurality of the processors are coupled with the test main machine so as to generate a plurality of test signals according the plurality of the control signals, wherein the plurality of the elements to be tested can generate a plurality of test results respectively according to the plurality of the test signals. The test system can test a plurality of ICs at the same time, thereby greatly improving efficiency of IC test.

Description

technical field [0001] The invention relates to a testing system, in particular to a testing system capable of testing multiple chips to be tested simultaneously. Background technique [0002] In order to ensure the quality of the integrated circuit (IC) when it is shipped, after the manufacturing process is completed, each IC is generally tested, and the manufacturer will determine whether the IC is qualified based on the test results of the IC, and Based on this, it is judged whether the IC can be supplied to downstream manufacturers. [0003] see figure 1 , figure 1 Shown is a schematic diagram of a general single chip for testing. like figure 1 As shown, the tester (Tester) 10 will control the measuring instrument 14 through the control command (Command) sent by the general purpose instrument bus (General Purpose Instrument Bus, GPIB) 12, and then measure the chip 16 to be tested through the measuring instrument 14, Finally, the test result T produced by the chip to...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28G01R31/3177G01R31/319
Inventor 滕贞勇许益彰黄杰威
Owner PRINCETON TECH CORP