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Semiconductor device and method for manufacturing the device

A device and spacer technology, applied in the field of semiconductor devices and their manufacturing that can improve device reliability

Inactive Publication Date: 2009-07-01
DONGBU HITEK CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to this porosity, W-bridges may appear between the filled metal patterns

Method used

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  • Semiconductor device and method for manufacturing the device
  • Semiconductor device and method for manufacturing the device
  • Semiconductor device and method for manufacturing the device

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0026] Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described in detail. example Figure 3A to Figure 3H A cross-sectional view of a method of manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0027] example Figure 3A As shown in , an STI region S for forming a device isolation film and a gate region G for forming a gate electrode are defined in the lower structure 100 . For example, lower structure 100 may be a silicon substrate or a silicon layer formed on and / or over an insulating film. In the following description, the substrate is the lower structure 100 . The STI region S and the gate region G may be formed by selectively removing the lower structure 100 . In the embodiment of the present invention, the depth h of the STI region S 2 can be compared to the depth h of the gate region G 1 big. The STI region S and the gate region G...

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PUM

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Abstract

A semiconductor device and a method for manufacturing the device capable of preventing an LDD region and a lower portion of the gate electrode from overlapping each other to achieve desirable device performance are disclosed. Embodiments relate to a semiconductor device and a method for manufacturing the device that may minimize overlap between an LDD region and a lower portion of the gate electrode. Minimizing overlap may maximize device performance and minimize the generation of defects between gate electrodes.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2007-0136172 (filed on December 24, 2007) based on 35 U.S.C119, the entire contents of which are hereby incorporated by reference. technical field [0002] The present invention relates to a semiconductor device and a manufacturing method thereof, more particularly, to a semiconductor device capable of improving device reliability and a manufacturing method thereof. Background technique [0003] Embodiments relate to a semiconductor device and a method of manufacturing the same, which can maximize reliability of the device. It may be desirable to minimize the size of transistors while allowing the number of transistors on a particular area to be maximized. However, when minimizing the size of the transistor, there is a limit to reducing the junction depth of the source / drain. [0004] When a semiconductor device is manufactured, as the channel changes from a relatively long channel to a short chan...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/82H01L21/336H01L27/02H01L29/78H10N80/00
CPCH01L21/26586H01L29/66606H01L29/7834H01L29/66621H01L21/32155H01L29/6659H01L29/4236H01L29/42368H01L29/7833
Inventor 金大均
Owner DONGBU HITEK CO LTD