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Multi-stage floating-point accumulator

An accumulator, floating-point technology, used in instruments, data transformation, calculations, etc., to solve problems such as limiting the speed at which the processor can operate

Inactive Publication Date: 2013-01-02
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The total time spent on these steps may limit the speed at which the processor can operate

Method used

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  • Multi-stage floating-point accumulator
  • Multi-stage floating-point accumulator
  • Multi-stage floating-point accumulator

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Embodiment Construction

[0015] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0016] Floating-point accumulation in one stage can be expressed as:

[0017] Σ i = 1 n X i = Σ i = 1 n - 1 X i + X n , For 1≤n≤N,

[0018] Equation (1)

[0019] where n is the index of the floating-point value being accumulated,

[0020] x n is the nth floating-point value being accumulated, where X 0 = 0, and

[0021] N...

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Abstract

A multi-stage floating-point accumulator includes at least two stages and is capable of operating at higher speed. In one design, the floating-point accumulator includes first and second stages. The first stage includes three operand alignment units, two multiplexers, and three latches. The three operand alignment units operate on a current floating-point value, a prior floating-point value, and a prior accumulated value. A first multiplexer provides zero or the prior floating-point value to the second operand alignment unit. A second multiplexer provides zero or the prior accumulated value to the third operand alignment unit. The three latches couple to the three operand alignment units. The second stage includes a 3-operand adder to sum the operands generated by the three operand alignment units, a latch, and a post alignment unit.

Description

technical field [0001] The present invention relates generally to electronic devices, and more particularly, to a floating point accumulator. Background technique [0002] In numeric processors, numerical data may be expressed using integer or floating-point representations. Floating point representations are used in many applications due to their ability to express a wide range of values ​​and their ease of manipulation for certain arithmetic operations. A floating-point representation usually consists of three components: a sign bit (sign), a mantissa (mant) (sometimes called a significand), and an exponent (exp). Floating point values ​​can be expressed as (-1) sign ×mant×2 exp . [0003] Floating point accumulation is an arithmetic operation that is typically performed for various applications such as graphics, digital signal processing, and the like. Floating-point accumulation typically requires (1) receiving an input floating-point value and an accumulated floati...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F7/485G06F7/509G06F5/01
CPCG06F7/5095G06F5/012G06F7/485G06F7/49936G06F2207/3884G06F5/01G06F7/509
Inventor 杜云于春焦国方
Owner QUALCOMM INC