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Clock signal generating circuit and digital circuit with same

A clock signal, digital circuit technology, applied in the direction of generating/distributing signals, logic circuit connection/interface layout, electrical components, etc., can solve problems such as signal synchronization problems

Active Publication Date: 2011-05-11
REALTEK SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Furthermore, such circuits are often greatly affected by process, voltage, and temperature changes (Process, Voltage, and Temperature, PVT), which causes problems in signal synchronization

Method used

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  • Clock signal generating circuit and digital circuit with same
  • Clock signal generating circuit and digital circuit with same
  • Clock signal generating circuit and digital circuit with same

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0022] Please refer to FIG. 1 , which illustrates a digital circuit system 100 according to an embodiment of the present invention. The digital circuit system 100 shown in FIG. 1 includes a logic circuit 102, a first cache unit 104, and a second cache unit 106, wherein the logic circuit 102 can be a part or all of circuits that constitute a specific digital logic operation, and by The first cache unit 104 disposed at its front end and the second cache unit 106 disposed at its rear end form the operation stage of the specific digital logic operation; that is, the circuit components 102-106 may form part of the pipeline architecture, and the digital data D. 1 That is, the data transmitted from the previous stage circuit and temporarily stored in the first cache unit 104, the digital data D 2 Then it is D temporarily stored in the first cache unit 104 1 The operation result obtained after the operation of the logic circuit 102 is temporarily stored in the second cache unit 106 ...

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PUM

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Abstract

The invention relates to a digital circuit system, which comprises a first buffer unit, an arithmetic unit, a second cache unit, a multi-phase clock signal generating unit, a first selector and a second selector, wherein the first buffer unit is used for receiving and temporarily storing digital data; the arithmetic unit is used for calculating and generating result data according to the digital data temporarily stored by the first buffer unit; the second buffer unit is used for receiving and temporarily storing the result data; the multi-phase clock signal generating unit is used for generating a plurality of reference clock signals, and different phases exist between the reference clock signals; the first selector is used for selecting one of the reference clock signals so as to output the first clock signal to the first buffer unit; and the second selector is used for selecting another reference clock signal so as to output the second clock signal to the second buffer unit.

Description

technical field [0001] The present invention relates to a clock signal generation circuit, in particular to a clock signal generation circuit which utilizes multi-phase clock signals to generate clock signals with specific time delays. Background technique [0002] In the technical field of digital logic operations, temporary storage components such as flip-flops are used to temporarily store the intermediate operation values ​​or results of digital logic operation circuits, and the so-called pipeline architecture formed accordingly (pipeline structure) is a very common implementation method, and the digital logic operation circuit formed in this way can be regarded as dividing its overall operation operation into multiple temporal operation stages by using multiple temporary storage components (stage), each of which is composed of a part of the logic operation circuit that constitutes a complete operation function. Generally speaking, the above-mentioned temporary storage ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/04H03L7/06H03L7/099H03K19/0175
Inventor 陈逸琳
Owner REALTEK SEMICON CORP