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Multi-core processor satisfying SystemC syntax

A technology of multi-core processors and processor cores, applied in the architecture with multiple processing units, electrical digital data processing, special data processing applications, etc., can solve problems such as difficult debugging of multi-core processors, lack of support for parallel languages, etc.

Active Publication Date: 2011-09-07
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] In order to overcome the defects of existing multi-core processors that are difficult to debug and do not support parallel languages, the present invention proposes a multi-core processor that meets the syntax requirements of SystemC

Method used

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  • Multi-core processor satisfying SystemC syntax
  • Multi-core processor satisfying SystemC syntax
  • Multi-core processor satisfying SystemC syntax

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Embodiment Construction

[0054] The following describes in detail a multi-core processor that meets SystemC syntax requirements provided by the present invention with reference to the accompanying drawings and specific embodiments.

[0055] Multi-core processors optimized for SystemC hope to use SystemC as a multi-core software development language. SystemC is an extended library of C++. In 1999, companies such as Cadence, Synopsys, ARM, etc. in the EDA industry jointly organized the development of an EDA language based on C++, and SystemC was born. In 2006, SystemC officially became an IEEE standard, becoming the third natural language after VHDL and Verilog supported by all EDA software.

[0056] SystemC can provide higher design efficiency and more effective design process, which can help solve the explosive complexity, market pressure, cost increase and other issues faced by the integrated circuit industry.

[0057] The SystemC language itself is an extension of C++. Therefore, although SystemC is curre...

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Abstract

The invention discloses a multi-core processor satisfying SystemC, which comprises an array formed by a plurality of exchanging units for exchanging data through connection, and a plurality of processing units connected with the exchanging units, used for processing data and comprising local resource units, wherein the processing units are connected to other processing units by an exchanging unitadapter and an exchanging unit array through the local resource units, and the local resource units comprise one or more of an event processing cell block of the SystemC, a first-in-first-out queue cell block of the SystemC and a mutual exclusion and semaphore cell block of the SystemC. Through the multi-core processor, the mapping supporting a SystemC syntax unit to resources in a chip is achieved so that the local resources can be applied to the resource sharing and the synchronization between any plurality of processing units and between the processing unites and peripherals.

Description

Technical field [0001] The present invention relates to a multi-core processor, and more specifically, the present invention relates to a multi-core processor that satisfies SystemC syntax requirements. Background technique [0002] In recent years, multi-core processor technology has developed vigorously. The main reasons are as follows: First, the design requirements; the cost of silicon is getting lower and lower, and the degree of integration is getting higher and higher. The multi-core regular structure can simply and effectively use more silicon area; second, the business Demand; multimedia services are becoming more and more complex, requiring higher and higher platform flexibility and processing performance, while also requiring power consumption to be kept within the allowable range. Multi-core processors can potentially provide the highest performance-to-power ratio, which can be higher Performance calculation and flexibility; third, time to market requirements; time t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/80G06F15/163G06F17/50G06F9/52
Inventor 陈曦黄毅刘祥张金龙刘玉东
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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