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Integrated circuit and its power management method

A technology of integrated circuits and circuits, applied in the direction of logic circuits, electrical components, pulse technology, etc., to achieve the effect of reducing complexity

Active Publication Date: 2010-03-03
CONVERSANT INTPROP MANAGEMENT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] However, as components range in device size from 250nm to 130nm or below, the current consumption of the device in standby mode (also known as static leakage) becomes a growing part of the integrated circuit power budget

Method used

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  • Integrated circuit and its power management method
  • Integrated circuit and its power management method
  • Integrated circuit and its power management method

Examples

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Embodiment Construction

[0024] As shown in the exemplary figures (where like reference numerals indicate like or corresponding elements in the figures), exemplary embodiments of systems and methods according to the present invention are described in detail below. However, it should be understood that the present invention can be implemented in various forms. For example, while minimizing static leakage of integrated circuits has been described herein, the aspects of the invention may also be implemented on circuits that are not contained within integrated circuits. Therefore, specific description disclosed herein is not to be interpreted as limiting, but as a basis for the claims and as a basis for teaching those skilled in the art to practice the invention in any suitably embodied system, structure, method, process or manner. representative basis.

[0025] figure 1 is a block diagram of an integrated circuit 100 implementing a system for minimizing static leakage according to one embodiment of the...

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Abstract

The invention provides an integrated circuit and its power management method. The integrated circuit comprises two power supply ends configured to supply power for the integrated circuit, wherein thepower supply end comprises a positive power supply end and a grounded end, and the voltage at the positive power supply end (VDD) and the voltage at the grounded end (VSS) limit the logic level rangetogether; a logic part selecting from one of a logic gate and a storage unit and including a sleep transistor which is in series connection with one of the power supply end; a voltage generator configured to selectively generate the voltage out of the logic level range; a circuit configured supply the voltage out of the logic level range to the sleep transistor in a power-saving mode period; and avoltage regulator configured in the power-saving mode period to control the voltage generator so as to completely reduce the leakage current of the sleep transistor and provided with an emulated sleep transistor. The invention can minimize the static leakage and reduce the complexity of the fabrication technology for the integrated circuit.

Description

[0001] The present invention is a divisional application of an invention patent application with the filing date of July 5, 2005, the application number of 200580026872.4, and the title of the invention "system and method for minimizing static leakage of integrated circuits". [0002] Cross References to Related Applications [0003] This application requires the title "Systems and Methods for I / O and Power Island Management and Leakage Control on Integrated Circuits" filed on July 9, 2004 Priority of U.S. Provisional Patent Application No. 60 / 586,565, which is hereby incorporated by reference. This application is also related to U.S. Patent Application No. 10 / 840,893, entitled "Managing Power on Integrated Circuits Using Power Islands," filed May 7, 2004, which is incorporated herein by reference . technical field [0004] The present invention relates generally to integrated circuits, and more particularly to systems and methods for providing negative voltages in integrate...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/00
Inventor 兰迪·卡普兰史蒂文·施瓦克
Owner CONVERSANT INTPROP MANAGEMENT INC
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