Method for optimizing area of mixed signal chip

Abstract

The invention discloses a method for optimizing the area of a mixed signal chip, which relates to the technical field of integrated circuit. The method of the invention comprises the following steps:(1) when designing an IP layout, separating resistors or capacitors out of the IP to reduce the IP area substantially; (2) arranging the prepared IP and other logic units to obtain the area of the whole chip; and (3) placing the resistors or the capacitors which are separated out on a chip power ring, under a pad or in a wiring area which is different from the metal layer used by the resistors orthe capacitors. Compared with the prior art, the invention ensures the IP performance and simultaneously reduces the IP area, further optimizes the chip area, does not generate a waste area, and savesthe numbers of the resistors and the capacitors.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a method for optimizing the area of ​​mixed-signal chips. Background technique [0002] At present, the digital layout method of an integrated circuit is to arrange the completed IP (module), IO (input and output) and logic units, so as to obtain the area of ​​the entire chip. The problem caused by this method is that there are a large number of capacitors and resistors in the well-made IP that is usually used, such as regulator (level shifter) or chargepump (charge pump). And these devices often occupy a larger area, which will make the completed IP area larger. When the chip is laid out, the size and area of ​​the IP are fixed, which will generate some wasted areas on the chip, resulting in a larger chip area. At the same time, devices such as capacitors or resistors in the IP are simulated separately from the chip, so the number of capacitors or resistors install...

AI Technical Summary

Problems solved by technology

The problem caused by this method is: in the well-made IP that is usually used, such as regulator (level shifter) or chargepump (charge pump), there are a large number of capacitors and resistors.

And these devices often occupy a larger area, which will make the completed IP area larger

When the chip is laid out, the size and area of ​​the IP are fixed, and some wasteful areas will be generated on the chip, resulting in a larger chip area

At the same time, devices such as capacitors or resistors in the IP are simulated separately from the chip, so the number of capacitors or resistors installed in this way is often greater than the actual needs of the chip

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