Information processing device and control method
A technology of processing device and control unit, applied in the direction of program control design, electrical digital data processing, instrument, etc., can solve the problem of large scale of MRF
Inactive Publication Date: 2011-11-30
FUJITSU LTD
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Problems solved by technology
[0020] In addition, another reason is that the scale of MRF is larger than that of WRF, and the frequency of soft errors caused by neutrons etc. in MRF is higher than that in WRF
Method used
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[0039] Hereinafter, an example of the embodiment will be specifically described with reference to the drawings.
[0040] figure 2 It is a functional block diagram showing the configuration of the CPU of the first embodiment. exist figure 2 In , the solid arrows represent instructions for control, and the hollow arrows represent the flow of data.
[0041] figure 2 The CPU 200 in FIG. 1 has a first register file 201 , a second register file 202 , and an arithmetic unit 203 . The first register file 201 has many entries and is relatively large in size. The CPU 200 is provided with a second register file 202 that copies and stores a part of the data stored in the first register file 201 so that data can be quickly read from the large-scale first register file 201 to the computing unit 203 . That is, the number of entries in the second register file 202 is smaller than the number of entries in the first register file 201 , and data of only a part of the entries in the first...
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An information processing device and control method, the processing device has: a first register file; a second register file, which stores part of the data stored in the first register file; and an arithmetic unit, which uses data read from the second register file performing an operation, and outputting the result of the operation as output data; and an instruction unit, which issues a write instruction and a first and second generation instruction, the write instruction is used to instruct to write output to both the first and second register files Data and its error detection code, the first and second occurrence indications are used to indicate the generation of pseudo-faults of the first and second register files respectively. The processing device further has: a first control unit, which issues a first generation instruction when receiving the write instruction and the first generation instruction; a first generation unit, which, when receiving the first generation instruction, The detection code generates the first pseudo-fault data and outputs it to the first register file; and the same second control unit and second generation unit.
Description
technical field [0001] The invention relates to a technology for simulating fault occurrence. Background technique [0002] It is known that in general information processing devices, there are mechanisms for detecting errors when a register file or the like fails to cause data errors, and various mechanisms for automatically correcting the detected errors and recovering from the failure state. In the inspection process of the trial production stage and the actual manufacturing stage of the information processing device, it is necessary to respectively confirm that the following mechanisms, including a mechanism for detecting errors using a parity check, detecting errors using an error correction code (ECC), and A mechanism for performing corrections, a mechanism for automatically re-executing instructions by hardware based on error detection, a mechanism for re-executing programs by interrupting software based on error detection, and the like. That is, these mechanisms nee...
Claims
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IPC IPC(8): G06F12/16
CPCG06F11/2236G06F9/30105G06F9/30138G06F9/30127G06F11/2215G06F9/3865G06F11/1064G06F11/07G06F11/28G06F12/16
Inventor 菅竜二
Owner FUJITSU LTD