Byte code buffer device for improving instruction fetch bandwidth of Java processor and using method thereof

Abstract

The invention relates to a byte code buffer device for improving the instruction fetch bandwidth of a Java processor and a using method thereof. In the invention, a byte code register, a multi-path selection module and a byte code buffer are sequentially connected; the input end of the byte code register is connected with an instruction memory, and the output end of the byte code buffer is connected with a decoding section of the Java processor; the input end of a control module is connected with the decoding section of the Java processor, and the output end of the control module is respectively connected with the byte code register, the multi-path selection module and the byte code buffer; and the byte code register has 32 bits, the byte code buffer has 64 bits, and high 4-bit bytes of the byte code buffer are connected with the decoding section of the Java processor. When the available space of the byte code buffer is not less than 4 bytes, the byte code buffer device of the invention reads 4 bytes from the register and transfers the 4 bytes to the correct position of the buffer through the multi-path selection module to enable the byte code to be executed to be always in high bytes completely, thereby reducing the access and storage times and improving the instruction fetch bandwidth.

Description

technical field [0001] The invention relates to a Java processor, in particular to a bytecode buffer device for improving the instruction fetch bandwidth of the Java processor and a method for using the same. Background technique [0002] Computer instruction sets are generally divided into two categories: one is a fixed-length instruction set, that is, regardless of the instruction type, it maintains the same length, and its advantage is that it can judge and fetch a complete instruction while fetching instructions. , which is convenient for the pipeline execution of instructions. The disadvantage is that the instructions occupy the same length, which is not conducive to saving instruction storage space. Fixed-length instruction sets are mostly used in simple instruction set computer (RISC) systems; the other type is variable-length instructions. Set, that is, different instructions have different lengths. Its advantage is that it can reduce the instruction length as much a...

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Problems solved by technology

[0002] Computer instruction sets are generally divided into two categories: one is a fixed-length instruction set, that is, regardless of the instruction type, it maintains the same length, and its advantage is that it can judge and fetch a complete instruction while fetching instructions. , which is convenient for the pipeline execution of instructions. The disadvantage is that the instructions occupy the same length, which is not conducive to saving instruction storage space. Fixed-length instruction sets are mostly used in simple instruction set computer (RISC) systems; the other type is variable-length instructions. Set, that is, different instructions have different lengths. Its advantage is that it can reduce the instruction length as much as possible, which is conducive to saving instruction storage space. Its disadvantage is that it cannot determine the complete length of the instruction while fetching the instruction. After decoding the opcode part, the subsequent part can be determined and read, which is not conducive to the pipeline execution of instructions, so it is mostly used in complex instruction set computer (CISC) systems

The feature of this method is that when the register set is large, it can provide better instruction prefetch performance, but instruction transfer will cause its utilization rate to drop, so it is necessary to determine the appropriate register set size, so that it can better satisfy the decoding requirements. Instruction fetching requirements for components can reduce the amount of hardware equipment

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