In view of the problem that the memory controller configuration in the related technologies is not flexible enough to cause high memory update costs, the present invention proposes to implement a memory controller through a Field Programmable Gate Array (FPGA) to control the memory. Because FPGA itself has strong configurability, it can adapt to memory configuration updates, and can also manage multiple memory banks at the same time, effectively improving design flexibility.
 The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
 In the embodiment of the present invention, a memory controller is provided. The memory controller according to the present invention can be implemented based on FPGA.
 Such as figure 1 As shown, the memory controller according to the embodiment of the present invention includes:
 Data channel interface module (may be called DDR2Controller DCI (Data ChannelInterface))1, used to convert the linear address of the access request from the memory read engine and/or memory write engine into (DDR2SDRAM) segments according to the particle specifications selected for the memory Address in the form of an address, and controls the storage of access requests and data to be written; specifically, when the memory write engine needs to access the memory, the data channel interface module 1 can perform address conversion on the access request and convert the converted access The request is stored in the address storage module 2. When the access request from the memory write engine is a write request, the data channel interface module 1 also needs to send a write enable signal to the data storage module 3, so that the data from the memory write engine The data to be written is written into the data storage module 3; in addition, the data channel interface module 1 can also be used to monitor the storage status of the address storage module 2 and the data storage module 3. There is no space in the address storage module 2 and the data storage module 3. When there is a storage space, the writing of data to the address storage module 2 and the data storage module 3 is stopped.
 The address storage module 2 is connected to the data channel interface module 1, and is used to store the access request converted by the data channel interface module 1 under the control of the data channel interface module 1;
 The data storage module 3 is connected to the data channel interface module 1, and is used to store the data to be written from the memory write engine under the control of the data channel interface module 1;
 The state machine module 4 (may be called DDR2Controller FSM) is connected to the address storage module 2 and the data storage module 3, and is used to send various memory operation commands and access requests stored in the address storage module 2 according to the internal state of the memory. In the case that the sent access request is a write request, the state machine module 4 needs to further control the scheduling of the data to be written stored in the data storage module 3; specifically, for the access request from the address storage module 2, the state machine module 4 After detecting these operation requests, the state machine needs to issue appropriate commands according to the internal state of the memory chip. Specifically, the state machine module 4 can send access commands to the address storage module 2 and the data storage module 3, and the address storage module 2 The request and address in the memory are read and sent to the memory. When data needs to be written to the memory, the state machine module 4 needs to send a read request to the data storage module 3 to read the data to be written, and then send it The read data to be written achieves the purpose of scheduling the data to be written, and the transmission of the data to be written does not pass through the state machine module;
 The physical interface module 5 (may be called DDR2Interface) is connected to the state machine module 4, the address storage module 2, and the data storage module 3, and is used to perform operation commands and write data sent by the state machine module 4 according to the data requirements of the memory Convert to meet the signal timing of DDR2, and convert the data read back from DDR2. That is to say, because the memory controller and the memory have different data requirements, the physical interface module 5 can convert the access request sent by the state machine module 4 and the data to be written according to the data requirements of the memory and send them to the memory (making the memory The data sent by the controller to the memory meets the data requirements of the memory), and is used to convert the data from the memory according to the data requirements of the memory controller and send it to the data channel interface module 1 (make the data sent from the memory to the memory controller meet the Data requirements of the memory controller).
 For the data sent from the memory, the physical interface module 5 can directly send the data to the data channel interface module 1 after converting the data, and the data channel interface module 1 can send the data to the memory read engine after simple processing.
 In the memory controller according to the present invention, both the address storage module 2 and the data storage module 3 may be First In First Out (FIFO) memories.
 The memory controller according to the present invention can control the second-generation Double Data Rate Two Synchronous Dynamic Random Access Memory (DDR2 SDRAM), and the memory controller according to the present invention can respond to external data DDR2 Small Outline Dual In-line Memory Module (Small Outline Dual In-line Memory Module, referred to as SODIMM). The read and write requests of large-capacity, multi-memory, and high-bandwidth memory module modules are based on the address of the read and write request. The memory bar issues corresponding operation commands to complete the correct reading and writing of the data of the memory bar.
 The present invention can use multiple FPGAs as carriers. For example, considering the drive capability of the Virtex5 series FPGA chip XC5VLX50T, 8 memory sticks can be controlled by two controllers, each of which controls 4 memory sticks, and each memory stick has a capacity of 512MB (or other Value, and can be expanded to 4GB or greater), the controller module needs to query the working status of the memory bank whose address hits before issuing the operation command (the query can be implemented by the state machine module), and then according to the current bank of the memory bank Jump to the working state and complete the corresponding operation.
 The functions of the above-mentioned modules will be described in detail below.
 (1) Data channel interface module
 The data channel interface module is used to interact with the data interfaces of the two functional modules of DDR2 Read Engine and DDR2 Write Engine. At the same time, it converts the linear access address of the internal data channel access request into memory (ie, DDR2 SDRAM) according to the configuration mode specified by the user. ) Segment address form. Based on the different Burst Length (BL) of DDR2 SDRAM, the data channel interface module can decompose the data channel operation into multiple DDR2SDRAM access requests, and these requests will be saved to the dedicated address FIFO (that is, the above In the address storage module), the data of each write request is stored in the dedicated data FIFO (that is, the above-mentioned data storage module). After the request and data are stored, other modules can be called from the corresponding storage module . In addition, the data channel interface module can also be used to control the data FIFO and send control signals to the data FIFO.
 Among them, after the data channel interface module converts the address of the read/write request, the correct bank number (bank Address), row address (Row Address), column address (Column Address), and chip select in the memory are obtained through decoding signal. The data channel interface module can also monitor and process the full and empty states of the address storage module and the storage space of the data storage module.
 (2) State machine module
 The state machine module is responsible for issuing corresponding commands to the DDR2SDRAM according to the internal state of the DDR2SDRAM chip, and can access the address FIFO for decoding processing according to read and write requests.
 Specifically, the DDR2SDRAM access operation requests of other functional modules in the memory controller according to the present invention are all stored in the address FIFO, and the state machine module needs to send these access requests to the DDR2SDRAM device. If it is a write request, you also need to read the data in the data memory and send the data to the DDR2SDRAM device.
 In order to improve the efficiency of memory bus data transmission and reduce the difficulty of pipeline design, the Burst Length can be determined as 8 in the design, and the operation mode in which the Burst operation is interrupted is not supported, so that the state machine module can be in 4 clock cycles Perform decoding to ensure sufficient decoding time.
 In addition, before using the DDR2SDRAM device, the state machine module also needs to be initialized according to the parameters of the DDR2SDRAM device. Moreover, according to the physical mechanism of the DDR2SDRAM device, in the process of use, the state machine module also needs to periodically refresh the DDR2SDRAM device to avoid data loss after the memory is powered off.
 The memory controller in the embodiment of the present invention supports the 4bank and 8bank designs of DDR2SDRAM devices, so the internal storage space of the DDR2SDRAM device can be divided into 4/8 banks, and the external access to the DDR2SDRAM device is based on the bank. According to the current status of the bank, different commands are allowed.
 The state machine module needs to read and write 8 DDR2SODIMM memory modules. Each memory module SDRAM particle has 4 banks. During operation, it is necessary to record the working status of a total of 32 banks. Each time a read/write request is received, it needs to be compared. The secondary request address and the address of the current active bank will send corresponding commands according to different comparison results. According to the driving capability of FPGA, two controllers can usually be used to manage these 8 memory banks, and each controller manages 4 of them, ie, such as figure 2 Management method shown. Such as figure 2 As shown, two memory controllers are implemented in one FPGA, and each memory controller manages 4 DIMM memory modules respectively. At this time, 8 memory addresses can be uniformly addressed, and read and write according to the address organization of the memory modules The access address is decoded, the chip selection is performed according to the decoded result, and the operation command is sent to complete the corresponding operation.
 Optionally, two FPGAs may be used to manage 8 memory banks, and each FPGA manages 4 memory banks.
 According to the data manual of DDR2SDRAM, in order to reduce the design difficulty of the memory controller of the present invention, the state of only 4 active banks can be recorded in the memory controller. If the addressed bank is consistent with the address of the current active bank, you can directly search If the address misses the active bank address, you need to determine how many banks are currently open. If less than 4 banks are open, you can continue to open a new bank. If 4 banks are already open, you need to close it One of the active bank, replace it with the new bank address, activate the new bank, and then issue the operation command.
 For the implementation of operations such as opening a bank, closing a bank, reading, and writing, refer to Table 1 below.
 Table 1
 As shown in Table 1, the following commands are mainly required for memory control: load mode (LOADMODE), refresh (REPRESH), self-refresh start (SELF REPRESH entry), self-refresh end (SELF REPRESH exit), single bank precharge ( Single bankPRECHARGE), all bank precharging (All bank PRECHARGE), bank activation (bank activate), writing (WRITE), reading (READ), writing by automatic precharging (WRITE with auto PRECHARGE), reading by automatic precharging (READ with autoPRECHARGE), no operation (NO OPERATION), device selection (DeviceDESELECT), power-down entry, power-down exit; in addition, BA in Table 1 represents bank address, and H represents high Level, L means low level, X means undefined (each manufacturer can configure it according to actual needs).
 Since the memory controller according to the embodiment of the present invention can perform operations such as refreshing, charging, pre-charging, and powering off (closing the bank) on the memory device, the memory controller according to the present invention may not support self-refresh entry (SELF REPRESH entry). ), self-refresh end (SELF REPRESHexit), through automatic precharge write (WRITE with auto PRECHARGE), through automatic precharge read (READ with auto PRECHARGE), power-down entry (Power-down entry), power-off end (Power- Commands such as down exit). Optionally, for device DESELECT, since its function is similar to NO OPERATION, it may or may not be supported.
 The DDR2 controller needs to complete initialization and task scheduling. In the specific design of the state machine module, three finite state machines can be used to implement it, namely, the main state machine, the initialization state machine, and the decoding state machine.
 Among them, the main state machine is mainly used to generate corresponding operation commands according to the command request and the current bank state, including operation commands such as read commands, write commands, refresh, and precharge. Due to the complicated timing of DDR2 access and strict timing requirements for each command, it is necessary to design the main state machine to access the given parameters in strict accordance with the requirements of the data manual to avoid data errors.
 The initialization state machine is mainly used to initialize and configure the parameters of the DDR2 memory when entering the initialization part after the system reset. After the initialization is completed, the DDR2 memory will enter the InitRst state and wait for the command to be sent. The initialization part is composed of 13 states in sequence and executed sequentially, and a small state machine can be additionally formed during implementation. The initialization state machine of the present invention can initialize the memory according to the initialization mode specified in the memory technology manual, and the specific processing process is similar, and will not be repeated here.
 The decoding state machine is mainly used to realize the command decoding, and according to the decoding result to determine the time to send the corresponding memory operation instruction. Specifically, the decoding state machine needs to decode the address according to the address FIFO address. For example, when managing DDR2 SODIMM memory, it can convert the linear address of each read and write request into the segment address form of DDR2 SODIMM, and Compare the bank number and row address currently accessed with the recorded bank number and row address to determine whether they are consistent, and send the corresponding operation request according to the comparison result.
 (3) Address storage module and data storage module
 The address storage module and the data storage module can be collectively referred to as the storage module, which contains a number of dedicated buffers for storing the DDR2 SDRAM address of the operation and writing data.
 Among them, the address storage module is used to store addresses and commands (for example, read/write commands) accessed by each DDR2 SDRAM. The data FIFO is used to store data for write access to DDR2 SDRAM, while data for read access does not need to be cached. The storage module module must record the empty and full status information of the FIFO for other modules to query. The write control signal for the data storage module and address storage module needs to be generated by the data channel interface module, and the read signal is generated by the state machine module.
 (4) Physical interface module
 The physical interface module is responsible for converting the internal signal of the memory control into the interface signal form of DDR2SDRAM, and also needs to convert the signal and data from the memory device. In order to compensate for the delay of different data lines, the physical interface module first needs to be trained before the data transmission is officially started.
 Specifically, the interface data of the memory controller according to the embodiment of the present invention can be designed to be 128-bit wide (the bit width can also be other values), and usually each access of DDR2 SDRAM is 64-bit with upper and lower edge output. Therefore, in physical When the interface module writes the accessed address (for example, including bank number, row address, and column address), access command, access data, and corresponding strobe signal to DDR2 SDRAM, it needs to be converted according to the requirements of DDR2 SDRAM.
 In addition, the circuit part of the physical interface module needs to consider the timing issues between the signals. Specifically, the internal clock of the memory control, the interface accompanying clock, and the DDR2 SDRAM clock must be consistent. The commands on the interface are output by the falling edge of the internal clock, DQ 270-degree phase-shifted clock output is adopted to meet the write alignment requirements of the accompanying clock and the command. In addition, the circuit part of the physical interface module needs to meet the preamble and postamble of the DQS signal, as well as the three-state enable signal generation for all bidirectional signals.
 It should be noted that the memory controller of the present invention can be used to control various types of memory, and the specific control method is similar to the above method, and will not be described here.
 In addition, how to program the FPGA to have the functions of the above-mentioned modules, how to select the FPGA as the memory controller according to the performance of the FPGA, and how to allocate the corresponding number of memory modules to each controller according to the performance of the memory controller. Those skilled in the art are well-known and will not be detailed here.
 To sum up, with the help of the technical solution of the present invention, a memory controller is implemented through FPGA to control the memory. Because FPGA itself has strong configurability, the memory controller can adapt to memory configuration updates. It can also manage multiple memory modules at the same time, effectively improving design flexibility and reducing costs.
 Obviously, those skilled in the art should understand that the above-mentioned modules or steps of the present invention can be implemented by a general computing device, and they can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. Above, alternatively, they can be implemented with program codes executable by a computing device, so that they can be stored in a storage device for execution by the computing device, or they can be made into individual integrated circuit modules, or they can be Multiple modules or steps are made into a single integrated circuit module to achieve. In this way, the present invention is not limited to any specific combination of hardware and software.
 The above are only preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various modifications and changes. Any modification, equivalent replacement, improvement, etc., made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.