Groove type power MOS device and manufacturing method thereof
A technology of MOS device and manufacturing method, which is applied in the direction of semiconductor/solid-state device manufacturing, semiconductor device, electrical components, etc., can solve the problems of reducing the voltage withstand reliability of the device, and achieve the effect of reducing the distance, reducing the cost and saving the processing cost.
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Embodiment 1
[0050] Such as figure 1 As shown: in the top view of the MOS device, the active region 1 is located in the central region of the semiconductor substrate, the active region 1 adopts a trench structure, and the conductive polysilicon 20 in the cell trench 7 passes through the active region 1 combined into a whole. figure 1The middle wavy line represents the source metal 25 covering the active region 1 . In order to clearly outline the structure of the active region 1 , the cell trenches 7 below the source metal 25 are all drawn with solid lines. In order to clearly show the structure of the gate terminal 2, the gate terminal trenches 8 under the gate metal 18 are all drawn in . In order to clearly show the first groove 9, the first side wall protection 10 and the second side wall protection 11 in the first groove 9; the first groove 9, the first side wall protection 10 and the second side wall protection 11 are represented by dotted lines. A terminal protection area 3 is pr...
Embodiment 2
[0056] image 3 and Figure 4 It is a schematic structural diagram of Embodiment 2 of the present invention, specifically another implementation of the terminal protection area 2 . in image 3 is a top view of either end of the MOS device, Figure 4 for image 3 The B-B section view. image 3 The middle wavy line represents the source metal 25 covering the active region 1 . In order to clearly show the first groove 9, the first side wall protection 10 and the second side wall protection 11 in the first groove 9; the first groove 9, the first side wall protection 10 and the second side wall protection 11 are represented by dotted lines. Such as image 3 As shown: the active region 1 is covered with a source metal 25 , the outer circle of the source metal 25 is provided with a gate metal 18 , and the gate metal 18 is not in contact with the source metal 25 . A first metal layer 17 is provided on the outer circumference of the gate metal 18 , and the first metal layer 17 is...
Embodiment 3
[0060] Figure 5 and Figure 6 It is a schematic structural diagram of Embodiment 3 of the present invention, specifically another implementation of the terminal protection area 3 . Figure 5 The middle wavy line represents the source metal 25 covering the active region 1 . In order to clearly outline the structure of the active region 1 , the cell trenches 7 below the source metal 25 are all drawn with solid lines. In order to clearly show the structure of the gate terminal 2, the gate terminal trenches 8 under the gate metal 18 are all drawn in . In order to clearly show the first groove 9, the first side wall protection 10 and the second side wall protection 11 in the first groove 9; the first groove 9, the first side wall protection 10 and the second side wall protection 11 are represented by dotted lines. Figure 5 is the top view of the MOS device, Figure 6 for Figure 5 C-C section view. Such as Figure 5 As shown: the active region 1 is covered with a source me...
PUM
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