Memory system and memory access method

Abstract

The invention discloses a memory system and a memory access method. The memory system comprises: a first processor that accesses memory according to a first clock frequency; a second processor that accesses memory according to a second clock frequency; a memory device configurable to selectively operate according to the first clock frequency or the second clock frequency; and a memory controller to enable dynamic configuration of organization of the memory device to allow a first portion of the memory device to be accessed by the first processor according to the first clock frequency and a second portion of the memory device to be accessed by the second processor according to the second clock frequency. The number of the required memory is reduced and the cost of the whole system is correspectively reduced.

Description

Technical field [0001] The invention relates to a memory system and a method for accessing the memory. Background technique [0002] A system on a chip (System On a Chip, SoC) has multiple embedded (embedded) processors, where each processor uses unique memory access timing and data bus width requirements when accessing the memory. In one implementation, two embedded processors each access a separate embedded memory module according to their native access timing scheme. In another implementation, two processors with different memory access timing schemes can use a bridging process to access a shared memory device. For example, if the first processor is designated to access the memory according to the first clock frequency, the second processor is designated to access the memory according to the second clock frequency, and the shared memory module is configured to access the memory according to the first clock frequency. The first processor accesses the shared memory module acco...

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Problems solved by technology

[0003] In the prior art, different memory access requests of different processors to access memory need to be converted from one clock domain to another, and multiple processors sharing the same memory device need to use a bridging process, which has a large delay, so the cost very high

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