Preparation method of dual damascene structure
A technology of dual damascene structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems affecting device transmission performance, increase in dielectric constant, increase in parasitic capacitance value, etc., and achieve high product yield , the effect of high stability and good dielectric properties
Inactive Publication Date: 2014-01-08
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology
[0006] However, the above method forms a stacked dielectric layer structure, resulting in an increase in the dielectric constant, which increases the parasitic capacitance and affects the transmission performance of the device.
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[0022] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar extensions without violating the connotation of the present invention, so the present invention is not limited by the specific implementations disclosed below.
[0023] Secondly, the present invention is described in detail using schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, and it should not be limited here. The protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be inc...
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Abstract
The invention relates to a preparation method of a dual damascene structure. The method comprises the following steps: forming a first dielectric material layer and a second dielectric material layer on a substrate in turn, wherein the second dielectric material layer is covered on the first dielectric material layer and the hardness of the second dielectric material layer is higher than that of the first dielectric material layer; forming grooves and pores on the first dielectric material layer and the second dielectric material layer respectively, depositing metal material in the grooves and pores; removing excess metal material and the second dielectric material layer to ensure that the surface of the first dielectric material layer has thin second dielectric material layer or does not have the second dielectric material layer. By adopting the method of the invention, under the premise of not increasing the process complexity, the probability that the first dielectric material layer with low hardness is scratched or worn is reduced and the element can have good dielectric property, high stability and product yield and good transmission performance.
Description
technical field [0001] The invention relates to semiconductor manufacturing technology, in particular to a method for manufacturing a double damascene structure. Background technique [0002] In the VLSI process, with the miniaturization of components and the increase of integration, the number of wires in the circuit continues to increase, and the parasitic effects generated by the resistance (R) and capacitance (C) in the wires have caused serious problems. Transmission delay (RC Delay). In order to reduce the transmission delay, people have carried out research and improvements in reducing resistance and reducing parasitic capacitance. For example, because metal copper has a high melting point, low resistance and high resistance to electromigration, most of the current metal copper is used to replace the commonly used in the past. metal aluminum. However, due to the limitations of the process and wire resistance, it is almost difficult to further reduce the parasitic ca...
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IPC IPC(8): H01L21/768
Inventor 周鸣牛孝昊
Owner SEMICON MFG INT (SHANGHAI) CORP